R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 344

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 DMA Controller (DMAC)
9.5.10
(1)
In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one
word, or one longword) is completed. One bus cycle or more by the CPU or DTC are executed in
the bus released cycles.
In figure 9.24, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer
mode by cycle stealing.
In figures 9.25 and 9.26, the TEND signal output is enabled and data is transferred in longwords
from the external 16-bit 2-state access space to the 16-bit 2-state access space in normal transfer
mode by cycle stealing.
In figure 9.25, the transfer source (DSAR) is not aligned with a longword boundary and the
transfer destination (DDAR) is aligned with a longword boundary.
In figure 9.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer
destination (DDAR) is not aligned with a longword boundary.
Rev. 2.00 Sep. 16, 2009 Page 314 of 1036
REJ09B0414-0200
Bφ
Address bus
RD
LHWR, LLWR
TEND
Normal Transfer Mode (Cycle Stealing Mode)
Figure 9.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing
Bus
released
Bus Cycles in Dual Address Mode
DMA read
cycle
DMA write
cycle
Bus
released
DMA read
cycle
DMA write
cycle
Bus
released
DMA read
cycle
Last transfer cycle
DMA write
cycle
Bus
released