R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 940

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 24 Power-Down Modes
24.8.3
In deep software standby mode, the ports retain the states that were held during software standby
mode. The internal of the LSI is initialized by an internal reset caused by deep software standby
mode, and the reset exception handling starts as soon as deep software standby mode is canceled.
The following shows the port states at this time.
(1)
Pins for the address bus, bus control signals (CS0, AS, HWR and LWR), and data bus operate
depending on the CPU.
(2)
Whether the ports are initialized or retain the states that were held during software standby mode
can be selected by the IOKEEP bit.
• When IOKEEP = 0
• When IOKEEP = 1
24.8.4
When the IOKEEP bit is 0, Bφ output is undefined for a maximum of one cycle immediately after
exit from deep software standby mode. At this time, the output state cannot be guaranteed. Even
when the IOKEEP bit is set to 1, Bφ output is undefined for a maximum of one cycle immediately
after the IOKEEP bit is cleared to 0 after deep software standby mode was canceled, and the
output state cannot be guaranteed. (See figure 24.3)
However, clock can be normally output by canceling deep software standby mode with the
IOKEEP bit set to 1 and then controlling the Bφ output with the IOKEEP and PSTOP1 bits. Use
the following procedure.
Rev. 2.00 Sep. 16, 2009 Page 910 of 1036
REJ09B0414-0200
Ports are initialized by an internal reset caused by deep software standby mode.
The port states that were held in deep software standby mode are retained regardless of the LSI
internal state though the internal of the LSI is initialized by an internal reset caused by deep
software standby mode. At this time, the port states that were held in software standby mode
are retained even if settings of I/O ports or peripheral modules are set. Subsequently, the
retained port states are released when the IOKEEP bit is cleared to 0 and operation is
performed according to the internal settings.
Pins for address bus, bus control and data bus
Pins other than address bus, bus control and data bus pins
Pin State on Exit from Deep Software Standby Mode
Bφ Operation after Exit from Deep Software Standby Mode