R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 320

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 DMA Controller (DMAC)
9.5.2
(1)
In normal transfer mode, one data access size of data is transferred at a single transfer request. Up
to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer
mode.
The TEND signal is output only in the last DMA transfer. The DACK signal is output every time a
transfer request is received and a transfer starts.
Figure 9.7 shows an example of the signal timing in normal transfer mode and figure 9.8 shows
the operation in normal transfer mode.
Rev. 2.00 Sep. 16, 2009 Page 290 of 1036
REJ09B0414-0200
Address B
Normal Transfer Mode
Address T
Transfer Modes
External request transfer in single address mode:
A
Auto request transfer in dual address mode:
A
Figure 9.7 Example of Signal Timing in Normal Transfer Mode
Bus cycle
TEND
DREQ
Bus cycle
DACK
Figure 9.8 Operations in Normal Transfer Mode
Read
DMA transfer
cycle
Write
Total transfer
size (DTCR)
DMA
Transfer
Read
Last DMA
transfer cycle
Write
DMA
Address T
Address B
B
B

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