R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 524

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 16-Bit Timer Pulse Unit (TPU)
12.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be
selected as the output level in response to compare match of each TGR.
Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle.
Designating TGR compare match as the counter clearing source enables the cycle to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
(a)
PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are
output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs
specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and
D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of
paired TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
(b) PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty cycle
registers. The output specified in TIOR is performed by means of compare matches. Upon counter
clearing by a synchronous register compare match, the output value of each pin is the initial value
set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value
does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with
synchronous operation.
Rev. 2.00 Sep. 16, 2009 Page 494 of 1036
REJ09B0414-0200