R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 681

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.5.2
Figure 16.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
16.12 shows an example of SCI operation for multiprocessor format reception.
MPIE
RDRF
RDR
value
MPIE
RDRF
RDR
value
Multiprocessor Serial Data Reception
1
1
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Start
bit
Start
bit
Figure 16.12 Example of SCI Operation for Reception
0
0
MPIE = 0
MPIE = 0
D0
D0
ID1
D1
D1
Data (ID1)
Data (ID2)
RXI interrupt
request
(multiprocessor
interrupt)
generated
RXI interrupt
request
(multiprocessor
interrupt)
generated
(a) Data does not match station’s ID
D7
D7
(b) Data matches station’s ID
MPB
MPB
1
1
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
processing routine
Stop
bit
Stop
bit
1
1
Start
bit
Start
bit
0
0
Section 16 Serial Communication Interface (SCI)
D0
D0
Rev. 2.00 Sep. 16, 2009 Page 651 of 1036
If not this station’s ID,
MPIE bit is set to 1
again
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt processing routine
D1
D1
Data (Data 1)
Data (Data 2)
ID2
ID1
D7
D7
MPB
MPB
0
0
RXI interrupt request is
not generated, and RDR
retains its state
Stop
bit
Stop
bit
1
1
MPIE bit set to 1
again
Idle state
(mark state)
Idle state
(mark state)
REJ09B0414-0200
Data 2
1
1

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