R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 128

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Exception Handling
5.7.2
The exception handling starts when a sleep instruction (SLEEP) is executed while the SSBY bit in
SBYCR is clear (= 0) and the SLPIE bit in SBYCR is set (= 1). The exception handling caused by
execution of a sleep instruction is always executable in the program execution state.
The following operations are performed by the CPU:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the sleep instruction is generated,
After execution of a sleep instruction, a bus master other than the CPU may have bus mastership.
In this case, the exception handling starts at the point when the CPU gets bus mastership after the
operation of the other bus master has ended.
Table 5.9 shows the state of CCR and EXR after execution of illegal instruction exception
handling. See section 24.10, Sleep Instruction Exception Handling, for details.
Table 5.9
[Legend]
1: Set to 1
0: Cleared to 0
: Retains the previous value.
Rev. 2.00 Sep. 16, 2009 Page 98 of 1036
REJ09B0414-0200
Interrupt Control Mode
0
2
the start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
Sleep Instruction
States of CCR and EXR after Sleep Instruction Exception Handling
I
1
1
CCR
UI



0
T
EXR
I2 to I0

7