R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 736

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I
17.4.6
The logic levels at the SCL and SDA pins are routed through the noise cancelers before being
latched internally. Figure 17.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The signal input to SCL
(or SDA) is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Rev. 2.00 Sep. 16, 2009 Page 706 of 1036
REJ09B0414-0200
(Master output)
(Master output)
(Slave output)
(Slave output)
processing
ICDRS
ICDRR
RDRF
SDA
SDA
SCL
SCL
User
Sampling clock
Noise Canceler
SDA input
SCL input
2
C Bus Interface 2 (IIC2)
or
Figure 17.12 Slave Receive Mode Operation Timing 2
A
9
System clock period
Figure 17.13 Block Diagram of Noise Canceler
Sampling clock
D
Bit 7
1
Latch
C
Bit 6
Data 1
2
Q
Bit 5
3
D
Bit 4
Sampling
4
clock
Latch
C
Bit 3
5
[3] Set ACKBT
Q
Bit 2
6
Bit 1
7
Compare
detection
match
circuit
[3] Read ICDRR
Bit 0
8
A
Internal SCL
internal SDA
9
or
[4] Read ICDRR
Data 1
Data 2