R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 689

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.19 shows a sample flowchart
for serial data reception.
[3]
No
No
Read receive data in RDR and
Clear ORER flag in SSR to 0
clear RDRF flag in SSR to 0
Overrun error processing
Read ORER flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
All data received
Error processing
Start reception
Figure 16.19 Sample Serial Reception Flowchart
Initialization
ORER = 1
RDRF = 1
<End>
<End>
Yes
Yes
No
(Continued below)
Error processing
Yes
[2]
[1]
[3]
[4]
[5]
[1] SCI initialization:
[2] [3] Receive error processing:
[4] SCI state check and receive data read:
[5] Serial reception continuation procedure:
Section 16 Serial Communication Interface (SCI)
The RxD pin is automatically designated as
the receive data input pin.
If a receive error occurs, read the ORER
flag in SSR, and after performing the
appropriate error processing, clear the
ORER flag to 0. Receive cannot be
resumed if the ORER flag is set to 1.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR
and clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
reading the RDRF flag, reading RDR, and
clearing the RDRF flag to 0 should be
finished. However, the RDRF flag is cleared
automatically when the DTC or DMAC is
initiated by a receive data full interrupt (RXI)
and reads data from RDR.
Rev. 2.00 Sep. 16, 2009 Page 659 of 1036
REJ09B0414-0200