R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 757

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5. The ADST bit is automatically cleared when A/D conversion is completed for all of the
18.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 18.5 shows the A/D conversion timing. Table 18.3 indicates
the A/D conversion time.
As indicated in figure 18.5, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in table 18.3.
Channel 0 (AN0)
Channel 2 (AN2)
Channel1 (AN1)
Channel 3 (AN3)
ADST
ADF
ADDRA
ADDRB
ADDRC
ADDRD
operation state
operation state
operation state
operation state
SPL
channels that have been selected. A/D conversion stops and the A/D converter enters a wait
state.
). The length of t
Note: * ↓ indicates the timing of instruction execution by software.
Input Sampling and A/D Conversion Time
Waiting for conversion
(One-Cycle Scan Mode, Three Channels (AN0 to AN2) Selected)
Waiting for conversion
D
Waiting for conversion
varies depending on the timing of the write access to ADCSR. The total
A/D conversion time
A/D conversion 1
Set *
Figure 18.4 Example of A/D Conversion
A/D conversion one-cycle execution
Transfer
A/D conversion 2
A/D conversion result 1
Waiting for conversion
D
A/D conversion 3
) passes after the ADST bit in ADCSR is set to
CONV
) includes t
Rev. 2.00 Sep. 16, 2009 Page 727 of 1036
A/D conversion result 2
D
and the input sampling time
A/D conversion result 3
Section 18 A/D Converter
Waiting for conversion
Waiting for conversion
Waiting for conversion
REJ09B0414-0200
Clear*