R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 118

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Exception Handling
Table 5.3
[Legend]
VBR:
Vector table address offset: See table 5.2.
5.3
A reset has priority over any other exception. When the RES pin goes low, all processing halts and
this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20
ms with the STBY pin driven high when the power is turned on. When operation is in progress,
hold the RES pin low for at least 20 cycles.
In addition to the RES pin, it is also possible to establish the reset state by two operations in the
internal circuit. One of them is to use an overflow in the watchdog timer. The other is to use an
external interrupt during deep software standby mode. For details, see section 4, Resets, section
15, Watchdog Timer (WDT), and section 24, Power-Down Modes.
A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules.
The interrupt control mode is 0 immediately after a reset. However, there are registers that will not
be initialized by issuing an internal reset based on the watchdog timer or by issuing an internal
reset based on the external interrupt during deep software standby mode. For details, see section 4,
Resets, section 15, Watchdog Timer (WDT), and section 24, Power-Down Modes.
Rev. 2.00 Sep. 16, 2009 Page 88 of 1036
REJ09B0414-0200
Exception Source
Reset, CPU address error
Other than above
Reset
Calculation Method of Exception Handling Vector Table Address
Vector base register
Calculation Method of Vector Table Address
Vector table address = (vector table address offset)
Vector table address = VBR + (vector table address offset)