R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 723

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
5
4
3
Bit Name
RDRF
NACKF
STOP
0
0
Initial
Value
0
R/W
R/W
R/W
R/W
Description
Receive Data Register Full
[Setting condition]
•
[Clearing conditions]
•
•
No Acknowledge Detection Flag
[Setting condition]
•
[Clearing condition]
•
Stop Condition Detection Flag
[Setting condition]
•
•
[Clearing condition]
•
When receive data is transferred from ICDRS to
ICDRR
When 0 is written to this bit after reading RDRF = 1
(When the CPU is used to clear this flag by writing
0 while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When data is read from ICDRR
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is set to 1
When 0 is written to this bit after reading NACKF =
1
(When the CPU is used to clear this flag by writing
0 while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
In master mode, when a stop condition is detected
after frame transfer
In slave mode, when a stop condition is detected
after a general call or after the slave address that
came as the first byte after detection of a start
condition has matched the address set in SAR
When 0 is written to this bit after reading STOP = 1
(When the CPU is used to clear this flag by writing
0 while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
Rev. 2.00 Sep. 16, 2009 Page 693 of 1036
Section 17 I
2
C Bus Interface 2 (IIC2)
REJ09B0414-0200