R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 49

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Classification
Bus control
Pin Name
BACK
BS-A/BS-B
AS
AH
RD
RD/WR
LHWR
LLWR
LUB
LLB
CS0
CS1
CS2-A/CS2-B
CS3
CS4
CS5-A/CS5-B
CS6-A/CS6-B
CS7-A/CS7-B
WAIT
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Description
Bus acknowledge signal, which indicates that the bus has
been released.
Indicates the start of a bus cycle.
Strobe signal which indicates that the output address on the
address bus is valid in access to the basic bus interface or
byte control SRAM interface space.
This signal is used to hold the address when accessing the
address-data multiplexed I/O interface space.
Strobe signal which indicates that reading from the basic
bus interface space is in progress.
Indicates the direction (input or output) of the data bus.
Strobe signal which indicates that the higher-order byte
(D15 to D8) is valid in access to the basic bus interface
space.
Strobe signal which indicates that the lower-order byte (D7
to D0) is valid in access to the basic bus interface space.
Strobe signal which indicates that the higher-order byte
(D15 to D8) is valid in access to the byte control SRAM
interface space.
Strobe signal which indicates that the lower-order byte (D7
to D0) is valid in access to the byte control SRAM interface
space.
Select signals for areas 0 to 7.
Requests wait cycles in access to the external space.
Rev. 2.00 Sep. 16, 2009 Page 19 of 1036
Section 1 Overview
REJ09B0414-0200