R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 505

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
2
1
Bit Name
TGFC
TGFB
Initial
value
0
0
R/W
R/(W)* Input Capture/Output Compare Flag C
R/(W)* Input Capture/Output Compare Flag B
Description
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always
read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Status flag that indicates the occurrence of TGRB input
capture or compare match.
[Setting conditions]
•
•
[Clearing conditions]
•
•
When TCNT = TGRC while TGRC is functioning as
output compare register
When TCNT value is transferred to TGRC by input
capture signal while TGRC is functioning as input
capture register
When DTC is activated by a TGIC interrupt while the
DISEL bit in MRB of DTC is 0
When 0 is written to TGFC after reading TGFC = 1
When TCNT = TGRB while TGRB is functioning as
output compare register
When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
When DTC is activated by a TGIB interrupt while the
DISEL bit in MRB of DTC is 0
When 0 is written to TGFB after reading TGFB = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Rev. 2.00 Sep. 16, 2009 Page 475 of 1036
Section 12 16-Bit Timer Pulse Unit (TPU)
REJ09B0414-0200