R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 202

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Bus Controller (BSC)
8.2.7
BCR1 is used for selection of the external bus released state protocol, enabling/disabling of the
write data buffer function, and enabling/disabling of the WAIT pin input.
Rev. 2.00 Sep. 16, 2009 Page 172 of 1036
REJ09B0414-0200
Bit
15
14
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
BRLE
BREQOE
Bus Control Register 1 (BCR1)
BRLE
DKC
R/W
R/W
15
0
7
0
BREQOE
Initial
Value
0
0
R/W
R/W
14

0
6
0
R/W
R/W
R/W
13


R
R
0
5
0
Description
External Bus Release Enable
Enables/disables external bus release.
0: External bus release disabled
1: External bus release enabled*
For details, see section 11, I/O Ports.
BREQO Pin Enable
Controls outputting the bus request signal (BREQO) to
the external bus master in the external bus released
state when an internal bus master performs an
external address space access.
0: BREQO output disabled
1: BREQO output enabled
BREQO pin can be used as I/O port
BREQ, BACK, and BREQO pins can be used as I/O
ports
12


R
R
0
4
0
R/W
11


R
0
3
0
R/W
10


R
0
2
0
WDBE
R/W

R
9
0
1
0
WAITE
R/W

R
8
0
0
0