R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 113

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4.4
This is a reset generated by the RES pin.
When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a
reset state. In order to firmly reset the LSI, the STBY pin should be set to high and the RES pin
should be held low at least for 20 ms at a power-on. During operation, the RES pin should be held
low at least for 20 states.
4.5
This is an internal reset generated when deep software standby mode is canceled by an interrupt.
When deep software standby mode is canceled, a deep software standby reset is generated, and
simultaneously, clock oscillation starts. After the time specified with DPSWCR has elapsed, the
deep software standby reset is canceled.
For details of the deep software standby reset, see section 24, Power-Down Modes.
4.6
This is an internal reset generated by the watchdog timer.
When the RSTE bit in RSTCSR is set to 1, a watchdog timer reset is generated by a TCNT
overflow. After a certain time, the watchdog timer reset is canceled.
For details of the watchdog timer reset, see section 15, Watchdog Timer (WDT).
4.7
Reading RSTCSR and RSTSR determines which reset was used to execute the reset exception
handling. Figure 4.2 shows an example the flow to identify a reset generation source.
Pin Reset
Deep Software Standby Reset
Watchdog Timer Reset
Determination of Reset Generation Source
Rev. 2.00 Sep. 16, 2009 Page 83 of 1036
REJ09B0414-0200
Section 4 Resets

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