R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 939

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24.8.2
Exit from deep software standby mode is initiated by signals on the external interrupt pins (NMI
and IRQ0-A to IRQ3-A), RES pin, or STBY pin.
1. Exit from deep software standby mode by external interrupt pins
2. Exit from deep software standby mode by the signal on the RES pin
3. Exit from deep software standby mode by the signal on the STBY pin
Deep software standby mode is canceled when any of the DNMIF and DIRQnF (n = 3 to 0)
bits in DPSIFR is set to 1. The DNMIF or DIRQnF (n = 3 to 0) bit is set to 1 when a specified
edge is generated in the NMI or IRQ0-A to IRQ3-A pins, that has been enabled by the
DIRQnE (n = 3 to 0) bit in DPSIER. The rising or falling edge of the signals can be specified
with DPSIEGR.
When deep software standby mode clearing source is generated, internal power supply starts
simultaneously with the start of clock oscillation, and internal reset signal is generated for the
entire LSI. Once the time specified by the WTSTS5 to WTSTS0 bits in DPSWCR has elapsed,
a stable clock signal is being supplied throughout the LSI and the internal reset is cleared.
Deep software standby mode is canceled on clearing of the internal reset, and then the reset
exception handling starts.
When deep software standby mode is canceled by an external interrupt pin, the DPSRSTF bit
in RSTSR is set to 1.
Clock oscillation and internal power supply start as soon as the signal on the RES pin is driven
low. At the same time, clock signals are supplied to the LSI. In this case, the RES pin has to be
held low until the clock oscillation has become stable. Once the signal on the RES pin is
driven high, the CPU starts reset exception handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Exit from Deep Software Standby Mode
Rev. 2.00 Sep. 16, 2009 Page 909 of 1036
Section 24 Power-Down Modes
REJ09B0414-0200