PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 98

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7.4
The internal micro controller is connected to an internal 24-Kbyte RAM, which holds both
code and data. This RAM is mapped to addresses 2000
stored in the following addresses:
•
•
Data is stored in addresses:
•
•
Full read and write access to both code and data in the RAM is enabled during the boot
loop (see
operation are valid in data segments only. Write access to code is denied.
A checksum mechanism automatically calculates the checksum for a specified area in
RAM. This mechanism can be used to verify that firmware was downloaded correctly. It
can be used during the boot loop or during normal operation.
The checksum mechanism is activated through user registers. To check a specific area
in RAM, do the following:
1. Write the requested start address into the
2. Write the size (number of bytes) in the block to check to the
3. Write the expected checksum value to the
4. Write 02
5. Poll the
7.5
After hard reset, the digital transceiver automatically starts the boot process in which
firmware is downloaded to RAM from EEPROM, provided that the firmware exists in
EEPROM and is valid.
If there is no valid firmware in EEPROM, the digital transceiver enters the boot loop.
During the boot loop, firmware may be downloaded to RAM through one of the
management interfaces or from the remote modem (from the LT to the NT). See
Boot Loop” on Page
Preliminary Data Sheet
2000
6000
5B00
7E00
5F68
from 5F69
through 5F6C
of the arithmetic sum of all the bytes in the block.
go to normal operation) to the
“RAM_ADDR” on Page 208
correct) or 01
H
H
H
H
H
:5AFF
:7DFF
.
:5FFF
:7FFF
“The Boot Loop” on Page
Internal RAM Management
The Boot Process
H
RAM_CMD_STS
(run checksum process) or 03
H
through 5F6A
H
H
H
H
H
H
. The value of the expected checksum should be the 2’s complement
(expected checksum not correct).
99.
H
.
register until its value is 00
for a description of all possible values.
99). During normal operation, read and write
RAM_CMD_STS
98
H
(run checksum process, and if successful
RAM_ADDR
RAM_CHKSUM
H
H
register from 5F67
Operation – Digital Block
through 7FFF
register at 5F6D
(expected checksum was
RAM_LENGTH
register from 5F6B
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827
H
, with code
H
through
H
register
. See
“The
H