PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 51

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 14
Signal Name Pin Name
RXD0
RXD1
RXD2
RXD3
RXDV
TXCLK
TXD0
TXD1
TXD2
TXD3
TXEN
1)
2.4.1.2
The Reduced Media Independent Interface (RMII) provides a low pin-count interface for
use between Ethernet PHYs and switch ASICs in high port density designs. MII uses 14
pins for data and control per port. RMII uses only six pins per port and one pin per switch
ASIC. The interface can be configured to operate as a MAC or PHY device.
Table 15
Signal Name Pin Name
REFCLK
RXD0
RXD1
RXDV
TXD0
Preliminary Data Sheet
Pins that control configuration during hard reset must be pulled up or pushed down with resistors, as required.
See
“Configuration Pins During Hard Reset” on Page 81
RMII Modes
MII PHY Mode Pins (page 2 of 2)
RMII MAC Mode Pins (page 1 of 2)
ETHOD0
ETHOD1
ETHOD2
ETHOD3
ETHCTLO
ECLK3
ETHID0
ETHID1
ETHID2
ETHID3
ETHCTLI
ECLK1
ETHID0
ETHID1
ETHCTLI
ETHOD0
P12
R12
M10
L9
Pin # I/O Function
P13
Pin #
L9
M14
M13
N15
M12
R13
R12
M10
P11
M9
P13
51
I
I
I
I
O
I/O Function
O
O
O
O
O
O
I
I
I
I
O
Reference Clock
Reception Data Input
Reception Data Input
Received Data Valid
Transmission Data Output
Configuration pin during hard reset.
Reception Data
Configuration pin during hard reset.
Reception Data
Configuration pin during hard reset.
Reception Data
Configuration pin during hard reset.
Reception Data
Configuration pin during hard reset.
Received Data Valid
Transmission Clock
Transmission Data
Transmission Data
Transmission Data
Transmission Data
Transmission Enable
and reference design document for details.
Pin and Signal Descriptions
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827
1)
1)
1)
1)
1)