PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 276

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PEF22827EL-V11

Manufacturer Part Number
PEF22827EL-V11
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF22827EL-V11

Lead Free Status / RoHS Status
Supplier Unconfirmed
Table 93
Parameter
Clock cycle time
SYNC setup time
SYNC hold time
Reception delay after rising edge of
clock (TXCLK)
Reception hold after rising edge of clock
(TXCLK)
Transmission setup time before rising
edge of clock (TXCLK)
Transmission hold time after rising edge
of clock (TXCLK)
12.5.5.4 Serial MII Interface, Source Synchronous Mode
Figure 50
MII interface. External load in SMII source mode is 40 pF.
Figure 50
Preliminary Data Sheet
TXCLK
Transmission
Signal
RXCLK
Reception
Signal
and
Typical Serial MII Interface Timing Parameters
Source Synchronous MII Interface Timing Diagram
Table 94
t
10
t
2
specify the timing characteristics of source synchronous Serial
t
3
t
1
t
1 2
t
13
t
4
Symbol
t
t
t
t
t
t
t
276
1
4
5
3
2
4
5
t
14
t
5
Electrical Characteristics - Overview
Min. Typ. Max.
8
0.77
0.45
2
0.7
0.71
t
1 5
Values
Synchronous_MII_Timing
8
4.7
Rev. 1.1, 2005-01-30
Unit Note
ns
ns
ns
ns
ns
ns
ns
VDSL6100i
PEF 22827
ECLK1
ETHCTLI
ETHOD0
ETHID0

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