PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 50

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.4.1.1
Table 13
Table 13
Signal Name Pin Name
COL
CRS
RXCLK
RXD0
RXD1
RXD2
RXD3
RXDV
TXCLK
TXD0
TXD1
TXD2
TXD3
TXEN
1)
Table 14
Signal Name Pin Name
COL
CRS
PHYCLK
RXCLK
Preliminary Data Sheet
Pins that control configuration during hard reset must be pulled up or pushed down with resistors, as required.
See
“Configuration Pins During Hard Reset” on Page 81
lists the MII MAC mode pins while
MII Modes
MII MAC Mode Pins
MII PHY Mode Pins (page 1 of 2)
COLI
CRSI
ECLK3
ETHID0
ETHID1
ETHID2
ETHID3
ETHCTLI
ECLK1
ETHOD0
ETHOD1
ETHOD2
ETHOD3
ETHCTLO
COLO
CRSO
ECLK1
ECLK2
Pin #
R11
N10
R13
R12
M10
P11
M9
P13
P12
L9
M14
M13
N15
M12
Pin #
P15
N14
P10
P12
50
Table 14
I/O Function
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I/O Function
O
O
I
O
Collision Detected
Carrier Sense
Reception Clock
Reception Data Input
Reception Data Input
Reception Data Input
Reception Data Input
Received Data Valid
Transmission Clock
Transmission Data
Configuration pin during hard reset.
Transmission Data
Configuration pin during hard reset.
Transmission Data
Configuration pin during hard reset.
Transmission Data
Configuration pin during hard reset.
Transmission Enable
Collision Detected
Configuration pin during hard reset.
Carrier Sense
MII Source Clock
Reception Clock
and reference design document for details.
lists the MII PHY mode pins.
Pin and Signal Descriptions
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827
1)
1)
1)
1)
1)