PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 72

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.6
In the digital transceiver, management and control are implemented by the following:
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4.6.1
An 8-bit internal micro controller is used to control the processes in the digital
transceiver. It establishes a user registers mechanism which the user can configure and
control the digital transceiver.
The internal micro controller is connected to internal ROM (16 Kbytes) and internal RAM
(24 Kbytes). ROM contains the kernel for carrying out the task of boot processing and
management interface control. RAM contains the rest of the code, for the task of
controlling the internal processes and user register management.
Firmware for the RAM can be loaded automatically from an EEPROM, or directly from
the parallel UART or MDIO management interface.
Firmware is loaded to the RAM during the boot process immediately after power-on. At
the conclusion of the boot process the digital transceiver enters normal operation mode.
4.6.2
User registers enable the user to configure and control the digital transceiver. Some are
accessible during the boot process, and all are accessible at the conclusion of the boot
process. For more information, see
4.6.3
The following management interfaces enable loading of firmware during the boot
process and access to user registers:
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Note: Use only one interface at a time.
See also,
Preliminary Data Sheet
Internal micro controller
Management interfaces
Configuration pins
EEPROM
JTAG
8-bit Parallel Interface
Serial Interface (UART)
MDIO Serial Interface
“Management Interfaces” on Page
Management and Control
Internal Micro Controller
User Registers
Management Interfaces
“The Boot Loop” on Page
72
Functional Description – Digital Block
135.
99.
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827