PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 163

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 33
between the PHY and the MAC, with the corresponding MII signal and the direction for
each. It also shows the external 25 MHz source clock required for correct operation that
must be connected to the ECLK2 pin (PHYCLK signal).
For mapping for these pins and signals, see
Page 50
Page
For functional descriptions of the corresponding MII signals, see reference [9].
Interface” on Page 274
Figure 33
9.3.2.3
A digital transceiver configured as a MAC that uses a Reduced Media Independent
Interface (RMII) to interface to a PHY provides a low pin count interface between
Ethernet PHYs and switch ASICs in high port density designs. RMII uses only six pins
for data and control per port plus one pin per switch ASIC, compared with MII, which
uses 14 pins per port.
This RMII interface is compatible with that described in reference [12]. For functional
descriptions of the RMII signals, see that document.
Preliminary Data Sheet
54.
and
shows the names of the pins (in parentheses) used for the MII interface
RMII Interface to a PHY in a MAC Configuration
Table 20 "Serial Management Interface (SMI) Pins for PHY Modes" on
Signals for PHY Configuration with MII Interface to a MAC
VDSL Digital
Transceiver
PHY
as a
specifies the AC characteristics of these signals.
PHYCLK
25 MHz
163
TXD[3:0]
RXCLK
TXCLK
RXD[3:0]
RXDV
TXEN
MDIO
MDCI
COL
CRS
Table 14 "MII PHY Mode Pins" on
IEEE 802.3
Compatible
Ethernet
Rev. 1.1, 2005-01-30
MAC
MII_signals_PHY
VDSL6100i
PEF 22827
Interfaces
“MII