PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 100

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

After download ends, start normal operation by setting the FW_DLOAD register at 5F6F
to 01
“Internal RAM Management” on Page
7.6
As soon as firmware is loaded and activated, normal operation starts and the appropriate
features become available. This section describes the features available.
The memory map for registers is described in
Digital Block” on Page
Register Descriptions – Digital Block” on Page
Two link environments are supported:
•
•
To select a link environment, set one of the values listed for the MAIN_MODE field (bits
2:0) of the
7.6.1
A standard compliant environment supports the following links:
•
Table 33
Parameter
Symbol rate
Constellation
Center Frequency
Interleaver
Frame format
•
•
Preliminary Data Sheet
Standard compliant
Boot - used to download firmware to the remote NT.
Default link - A default link is established after a cold start. Its parameters are as
defined in the standard and listed in
Alternate default links - Infineon VDSL supports two additional default profiles
(DF_STP1 and DF_STP2), in addition to the primary one (DF_STP0), to enable the
modem to overcome critical bridge taps and interference. Initially, the LT or NT tries
to establish a link using the primary default, DF_STP0. If this link fails, the modem
automatically switches to the next DF_STP. The STP that enables establishment of
the link becomes the new DF_STP. See also,
Mapping in EEPROM” on Page 92
Target Link - A target link is established for transmission of data. It is defined by
setting the target profile to the desired value in the LT.
H
. To verify the checksum of the code before starting normal operation mode, see
MAIN_MODE
Application Management
Standard Compliant Links
Default Link Parameters in Standard Compliant Environment
1 Downstream
675 kbaud
4
1.350 MHz
Disabled
Single Latency
register (8F01
171. For detailed descriptions of registers, see
2 Downstream
0
-
-
H
Table
and
). See
98.
100
“Current and Target STPs” on Page
33.
“Memory and Register Descriptions –
Page 186
“DF_STP1 and DF_STP2 Parameter
185.
1 Upstream
742.5 kbaud
4
4.455 MHz
for details.
Operation – Digital Block
Rev. 1.1, 2005-01-30
2 Upstream
0
-
-
VDSL6100i
PEF 22827
“Detailed
104.
H