PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 145

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 49 Serial Management Interface (SMI) Registers (PHY Mode) (page 2 of 2)
9.2.3.3
The Serial Management Interface (SMI) uses three 16-bit proprietary OEM registers in
the SMI address space to gain access to the internal address space. The function of
each OEM register is:
•
•
•
A write transaction into an internal register is performed as follows:
1. The host writes the internal address into the internal address register.
2. The host writes eight bits of data into bits 15:8 of the OPCDR register (at 11
3. The SMI asserts the BUSY status bit (bit 7) in the OPCDR register.
4. When the write operation into the internal register is complete, the SMI clears the
Note: The user must verify that a new write transaction does not override an old write or
The sequence of operations of a read transaction from an internal register is:
1. The host writes the internal address into the address register.
2. The host sets the Read opcode register bit to 1.
3. The SMI asserts the BUSY status bit.
4. The host polls the opcode register to check the Busy status bit. Once the Busy status
9.2.3.4
The 16-bit internal registers provide access to the MII SMI register set of the attached
Ethernet PHY. Access to these registers triggers the appropriate access process
through the MII SMI access registers. This simplifies access of a host to the standard MII
SMI register set.
Table 50
registers in MAC mode. For detailed descriptions of each register, see the page
indicated in the
Preliminary Data Sheet
SMI Address
12
13
H
H
Address pointer into the internal address space
Opcode/status register
Result register
the Write opcode register bit to 1.
BUSY status bit.
bit is clear, the requested data in the Result register is valid.
:1F
read command. To avoid overriding commands, poll the BUSY status bit to verify
that it is cleared before any new transaction with the internal registers.
H
shows memory mapping and the location of detailed descriptions of the SMI
Accessing Internal Memory Space through the SMI
SMI Registers (MAC Mode)
Detailed Description of SMI Registers
Mnemonic
RSLTR
Register Description
Result
Reserved
145
section.
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827
Interfaces
H
), setting
Pg
154
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