PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 73

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PEF22827EL-V11

Manufacturer Part Number
PEF22827EL-V11
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF22827EL-V11

Lead Free Status / RoHS Status
Supplier Unconfirmed
4.6.4
Several pins function as configuration pins in addition to their normal tasks. After power
is turned ON, and before these pins assume their normal function, the value of the pins
is sampled to determine the configuration.
Make sure that these pins are pulled down or up, as required, to define the required
configuration. See also,
4.6.5
The digital transceiver can be connected directly to an EEPROM device through a
standard serial I
Kbyte EEPROMs.
The EEPROM holds firmware to be downloaded to RAM, and other initialization
parameters. An EEPROM is usually included in NT systems in which a host processor
is not used. In LT systems that have a host processor on board, the EEPROM is not
required because firmware and other configuration parameters can be programmed
from the host. See also,
4.6.6
The test logic consists of a boundary scan register and other building blocks, and is
accessed through a Test Access Port (TAP). The TAP includes the TCK, TMS_A,
TMS_D, TDI_A, TDI_D, TDO_A and TDO_D pins.
The Test Clock input pin (TCK) provides the clock for the test logic. The test logic at the
Test Data Input (TDI_A and TDI_D) pins receives the serial test instructions and data.
The Test Data Output (TDO_A and TDO_D) pins are the serial output pins for test
instructions and data from the test logic. The data pins (TDI_A and TDO_D) ensure serial
movement of test data through the circuit. See
Page
The signals received at the Test Mode Select (TMS_A and TMS_D) input pins are
decoded by the TAP controller to control test operations.
Preliminary Data Sheet
134.
Configuration Pins
EEPROM
JTAG Interface
2
C interface. The digital transceiver supports both 32-Kbyte and 64-
“Configuration Pins During Hard Reset” on Page
“EEPROM” on Page
73
Functional Description – Digital Block
83.
“JTAG Interface (Boundary Scan)” on
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827
81.

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