PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 79

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.7
When the VDSL system operates in LT Mode (master mode), either the internal crystal
(DCXO) or an external clock can generate the master clock. If an external clock is used
to generate the master clock, the external clock is connected instead of the crystal. In
NT mode (Slave Mode) the clock frequency is derived from the receive signal.
On the LT side, the clock frequency is fixed. On the NT side the clock frequency is
controlled by the DCXO within a timing recovery loop. The clock can be tuned in a range
of 120 ppm in increments of < 5 ppm.
The accuracy of the externally connected crystal or the external clock is 50 ppm, as
specified in the ETSI and ANSI standards. Depending on the desired system
configuration, frequencies between 25 MHz and 38.88 MHz are possible. (See
“Operating Range – Analog Block” on Page
5.8
All digital circuits are reset to zero or to their default state with the RESET signal. RESET
is active low and has a circuit that prevents glitches. RESET should remain low for a
minimum of 200 ns to generate a reset.
Preliminary Data Sheet
Clock Generation
Reset
79
Functional Description – Analog Block
281.)
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827