PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 164

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PEF22827EL-V11

Manufacturer Part Number
PEF22827EL-V11
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF22827EL-V11

Lead Free Status / RoHS Status
Supplier Unconfirmed
The block diagram of the digital transceiver when it is configured as a MAC and uses
RMII to interface to a PHY is the same as for MII, as shown in
MAC Configuration with MII Interface to a PHY, on page
Figure 34
between the MAC and the PHY, with the corresponding RMII signal and the direction for
each. It also shows the external 50 MHz source clock required for correct operation that
must be connected to the REFCLK signal on pin ECLK1 (pin 60).
For mapping for these pins and signals, see
Page 51
Page
signals.
Figure 34
9.3.2.4
A digital transceiver configured as a PHY that uses a Reduced Media Independent
Interface (RMII) to interface to a MAC provides a low pin count interface between
Ethernet PHYs and switch ASICs in high port density designs. RMII uses only six pins
for data and control per port plus one pin per switch ASIC, compared with MII, which
uses 14 pins per port.
This RMII interface is compatible with that described in
descriptions of the RMII signals, see that document.
The block diagram of the digital transceiver when it is configured as a PHY and uses
RMII to interface to a MAC is the same as for MII, as shown in
Diagram of PHY Configuration with MII Interface to a MAC, on page
Preliminary Data Sheet
54.
and
“RMII Interface” on Page 274
shows the names of the pins (in parentheses) used for the RMII interface
RMII Interface to a MAC in a PHY Configuration
Table 19 "Serial Management Interface (SMI) Pins for MAC Modes" on
VDSL Digital
Transceiver
Signals for MAC Configuration with RMII Interface to a PHY
MAC
as a
RXD[1:0]
164
TXD[1:0]
MDCO
RXDV
TXEN
MDIO
specifies the AC characteristics of these
Table 15 "RMII MAC Mode Pins" on
REFCLK
50 MHz
162.
For detailed functional
Figure 31, Signals for
IEEE 802.3
Compatible
Ethernet
RMII_signals_MAC
PHY
Rev. 1.1, 2005-01-30
Figure 32, Block
162.
VDSL6100i
PEF 22827
Interfaces

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