PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 57

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

VDSL6100i
PEF 22827
Functional Overview
3.5
JTAG Interface
The test logic consists of a boundary scan register and other building blocks, and is
accessed through a Test Access Port (TAP). The TAP includes the TCK, TMS_A,
TMS_D, TDI_A, TDI_D, TDO_A and TDO_D pins.
The Test Clock input pin (TCK) provides the clock for the test logic. The test logic at the
Test Data Input (TDI_A and TDI_D) pins receives the serial test instructions and data.
The Test Data Output (TDO_A and TDO_D) pins are the serial output pins for test
instructions and data from the test logic. The data pins (TDI_A and TDO_D) ensure serial
movement of test data through the circuit. See also,
“JTAG Interface (Boundary
Scan)” on Page
134.
The signals received at the Test Mode Select (TMS_A and TMS_D) input pins are
decoded by the TAP controller to control test operations.
Preliminary Data Sheet
57
Rev. 1.1, 2005-01-30