PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 134

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

9
This chapter describes the following interfaces:
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9.1
Boundary Scan is implemented according to the IEEE 1149.1 standard.
the signals used for this purpose.
Table 41 Boundary Scan Interface
Symbol
TRST
TCK
TMS_D
TMS_A
TDI_D
TDI_A
TDO_D
TDO_A
The Test Clock input pin (TCK) provides the clock for the test logic. Serial test
instructions and data are received by the test logic on Test Data Input (TDI_D for digital
and TDI_A for analog). Test Data Output (TDO_D for digital and TDO_A for analog) is
the serial output for test instructions and data from the test logic.
The data pins (TDI_D, TDO_D, TDI_A and TDO_A) ensure serial movement of test data
through the digital or analog circuit. The signal received at the Test Mode Select (TMS_D
for digital and TMS_A for analog) input pin is decoded by the internal TAP controller to
control test operations.
To perform a boundary test of the entire integrated circuit, connect the Digital and Analog
Blocks externally. Do one of the following:
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Preliminary Data Sheet
JTAG Interface (Boundary Scan)
“Management Interfaces” on Page 135
“Network Interfaces” on Page 156
“EOC Interface” on Page 167
“I
Connect TDI_A to TDO_D
Connect TDO_A to TDI_D
2
C Interface for EEPROM” on Page 169
Interfaces
JTAG Interface (Boundary Scan)
Name
Test Reset
Test Clock
Digital Test Mode Select
Analog Test Mode Select
Digital Test Data IN
Analog Test Data IN
Digital Test Data Out
Analog Test Data Out
134
Function
TAP Controller with instruction,
bypass and identification register
Boundary scan chain
Rev. 1.1, 2005-01-30
Table 41
VDSL6100i
PEF 22827
Interfaces
shows