PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 144

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

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9.2.3.2
SMI registers include the following:
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Table 49
registers in PHY mode. For detailed descriptions of each register, see the page indicated
in the table, in the
Table 49 Serial Management Interface (SMI) Registers (PHY Mode) (page 1 of 2)
Preliminary Data Sheet
SMI Address
00
01
02
04
05
08
10
11
H
H
H
H
H
H
H
H
Preamble - A string of at least 32 consecutive ones (1) on MDIO, optional.
SFD - Start of Frame Delimiter.
OP - Opcode.
PHY Address - Defined by configuration pins as described in
During Hard Reset” on Page
Register Address - Register to be read from or written to.
Turnaround - Idle time that enables the MDIO driver to switch from the MAC to the
PHY for register reads. The MAC drives 10 during this time for writes, or ZZ for reads.
During turnaround, no device should drive MDIO. The PHY begins driving 0 on the
second bit of the turnaround period.
Data - 16-bit write or read data, as determined by the opcode.
Idle - The MAC and the PHY put MDIO in tristate during transfer of this bit, and the
pull-up resistor pulls it to a logical 1.
Standard registers (addresses 00
described in the IEEE 802.3 standard to support basic control and status, PHY
identifier and automatic negotiation operations.
Internal memory access registers (addresses 10
host to access registers in internal memory space.
Extended PHY capabilities registers (addresses 13
PHY capabilities.
:03
:0F
H
H
shows memory mapping and the location of detailed descriptions of the SMI
SMI Registers (PHY Mode)
Mnemonic
BMCR
BMSR
OUI
ANAR
ANLPAR
-
IADDSR
OPCDR
“Detailed Description of SMI
Register Description
16-bit Basic Mode Control
16-bit Basic Mode Status
32-bit Organizationally Unique Identifier
Automatic Negotiation Advertisement
Automatic Negotiation Link Partner Ability
Not implemented
Internal Address Space
Opcode
81.
H
through 05
144
Registers” section.
H
) include the SMI standard registers
H
H
through 12
through 14
H
“Configuration Pins
H
) enable an external
) support proprietary
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827
Interfaces
Pg
146
148
149
150
151
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152
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