PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 42

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 4
Pin or
Ball No.
P9
R10
K14
R8
R9
D15
R7
H11
H13
H12
H14
J13
Preliminary Data Sheet
Name
EOC_RCLK
EOC_RDATA O
EOC_REN
EOC_TCLK
EOC_TDATA I
EOC_TEN
NTR
PCM_RCLK
PCM_RDATA I
PCM_RSIG
PCM_RSYN
C
PCM_TDATA O
EOC and PCM Pins (page 1 of 2)
Pin
Type
I
O
I
O
I/O
I
I
I
PD
Buffer
Type
PD
PU
PD
-
PD
-
-
-
-
-
-
2)
3)
2)
2)
2)
42
Function in Normal Mode
Clear Channel Reception Clock
Configuration pin during hard reset.
EOC Reception Data
See also,
(LEDs)” on Page
Configuration pin during hard reset.
Clear Channel Reception Enable
Configuration pin during hard reset.
Clear Channel Transmission Clock
Configuration pin during hard reset.
EOC Transmission Data
Configuration pin during hard reset.
Clear Channel Transmission Enable
Configuration pin during hard reset.
Network Timing Reference
LT receives this 8 kHz clock. NT transmits
a sample of this 8 kHz division clock.
Can be configured as an independent
8 kHz output clock. Useful for the PCM
interface.
Configuration pin during hard reset.
PCM Reception Clock
Must be 0 during reset.
PCM Reception Serial Data
Must be 0 during reset.
PCM Reception Serial Signaling
Must be 0 during reset.
PCM Reception Synchronization
Signal
Must be 0 during reset.
PCM Transmission Serial Data
Configuration pin during hard reset.
4)
“External Status Signals
Pin and Signal Descriptions
131.
4)
Rev. 1.1, 2005-01-30
1)
4)
VDSL6100i
PEF 22827
4)
4)
1)
1)
1)
1)
1)
1)
1)
1)