PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 36

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 1
Pin or
Ball No.
N9
N10
N11
N12
N13
N14
N15
P1
P2
P3
P4
P5
P6
Preliminary Data Sheet
Name
UTID6
RXSYNC_EN I
CRSI
CRS
MDCI
MDC
MDCO
RXCLK
MDC
UTOD7
CRSO
CRS
ETHOD3
TXD3
RXD3
HRST_A
TDI_A
XTAL2
CLKOUT
BOOT_EN
Int
I/O Signals (page 12 of 15)
Pin
Type
I
I
I
I
I
O
O
O
O
O
O
O
O
O
AI
AI
AO
O
-
-
Buffer
Type
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PU
-
2)
36
Function
See description of signal using this pin.
Source Synchronous SMII Mode
Enables RXSYNC signal synchronization
Carrier Sense Input
Ethernet MII MAC - Carrier Sense
MDIO and SMI PHY Input Clock
Management Data Clock
MDIO and SMI MAC Clock Output
Reset value is 0.
Source Synchronous SMII - RX Clock
Management Data Clock
Not Used
Carrier Sense Output
Ethernet Interface MII PHY - Carrier
Sense
Ethernet Network Interface Output Data
Configuration pin during reset.
Ethernet Interface MII MAC - TX Data
Ethernet Interface MII PHY - RX Data
Analog Hard Reset
Analog JTAG Test Serial Data In
Tied to 0 in normal mode. For testing only.
Crystal
Not connected for CLK_MODE (L5) = 1.
Clock Output
Reference clock for parallel port and
internal use. Provides clock to the host.
Termination point must be active.
Boot Link Enable
Configuration pin during hard reset. Do not
use during normal operation.
Internal Use Only
Do not connect.
Pin and Signal Descriptions
Rev. 1.1, 2005-01-30
1)
VDSL6100i
PEF 22827
1)