PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet
PEF22827EL-V11
Specifications of PEF22827EL-V11
Related parts for PEF22827EL-V11
PEF22827EL-V11 Summary of contents
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VDSL6100i Int DSL M ode m-on ...
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ABM , ACE , AOP , ARCOFI ® ® FALC , GEMINAX , IDEC ® ® MUSAC , MuSLIC , OCTAT ® ® SCOUT , SICAT , SICOFI ® ® 10BaseV , 10BaseVX Technologies AG. Microsoft of ...
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VDSL6100i Revision History: Previous Version: Page Subjects (major changes since last revision) Update of Terminology, Register list and definitions, etc. 2005-01-30 None, First Release Rev. 1.1 ...
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Preface The PEF 22827 is an integrated VDSL modem-on-chip. It combines all the required functionality for standard 4-band VDSL over a twisted pair. This modem-on-chip includes a digital data transceiver supporting Ethernet interface, an analog front end (AFE) handling the ...
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Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.4.1.1 Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 6 Functional Description – Line Driver Block . . . . . . . . . . . . . . . . . . . . . 80 6.1 Functional Block Diagram – Line Driver . ...
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Table of Contents 7.6.8 Implementing Long Reach VDSL Manually . . . . . . . . . . . . . . . . . . . . . 123 7.6.9 Accessing the Remote Transceiver . . . . ...
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Table of Contents 10.4.1 Main Control Register (MAIN_CTL 185 10.4.2 Main Operation Mode ...
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Table of Contents 10.10.5 EEPROM Command Register (EEP_COMMAND 213 10.10.6 EEPROM Status Register (EEP_STATUS ...
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Table of Contents 10.15.3 PBO US2 Distance Register (PBO_US2D 236 10.15.4 PBO Maximum PSD Register (PBO_MAXPSD ...
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Table of Contents 11.2.12 PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Ethernet over VDSL CPE Application Example . . . . . . . . . . . . . . . . . . 21 Figure 2 Logic Symbol . . . . . . ...
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List of Figures Figure 43 Parallel Port Register Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Figure 44 Parallel ...
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List of Tables Table 1 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 43 Serial Port Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 85 JTAG Boundary Scan Timing Parameters . . . . . . . . . . . . . . . . . . . . . 268 Table 86 Absolute Maximum Ratings – Digital Block ...
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Integrated VDSL Modem-on-Chip VDSL6100i Version 1.1 1 Product Overview The PEF 22827 modem-on-chip is a single port integrated QAM based VDSL transceiver, whose technology complies fully with all current standards for VDSL - including ITU-T and ETSI. This IC integrates ...
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The compact design and low foot print of the VDSL6100i make it a preferred solution for the design of a Central Office (CO) or Customer Premises Equipment (CPE). 1.1 Features Features of the PEF 22827 include: • Highly integrated QAM ...
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Power The following are the power characteristics and features: • Typical power dissipation 0.95 Watt • Input voltages 1.2, 1.8, 3.3 and 5 • Fast warm start after power down • Power Save modes – Sleep mode – Wake-up ...
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Pin and Signal Descriptions Figure 2 shows the logic symbol of the PEF 22827. CLKIN HRST WAKEUP NTR EOC_TCLK EOC_TDATA EOC_RCLK EOC_RDATA EOC_TEN EOC_REN DAC[12:0] ADC[11:0] ADC_CLK UTID6 ETHID[3:0] COLI CRSI ETHCTLI ECLK2 UTICTL4 UTITXA[4:0] MDCI MDIO PA[3:0] PD[7:0] ...
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Pin Diagram Refer to one of the following sections to determine the pin associated with each signal. • “Master Pin List” on Page 25 • “Pin Lists by Function” on Page 39 • “Pin and Signal Assignment in Different ...
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GPO_ GPO_ 1 Res Res A2 A5 VDDI GPO_ 2 Res Res O_33 A1 VDDI 3 Res Res Int O_33 VSPL 4 Res Res Int US VSPL 5 Res Res OUT1 US VSPL 6 Res Res ...
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Master Pin List Table 1 lists and describes the pins of the PEF 22827. Table 1 I/O Signals (page 1 of 15) Pin or Name Ball No. A1 Res A2 Res A3 Res A4 VSPLUS A5 VSPLUS A6 VSPLUS ...
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Table 1 I/O Signals (page 2 of 15) Pin or Name Ball No. B7 Res B8 Res B9 Res B10 Res B11 Res B12 Res B13 Res 2 B14 I CD B15 VDD_PLL_12 PWR C1 GPO_A2 C2 VDDIO_33 C3 VDDIO_33 ...
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Table 1 I/O Signals (page 3 of 15) Pin or Name Ball No. 2 C14 I CCLK C15 VDD_PLL_12 PWR D1 GPO_A5 D2 GPO_A1 D3 Int D4 Int D5 OUT1 D6 INN1 D7 INP1 D8 VSMINUS D9 PD3 D10 PD5 ...
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Table 1 I/O Signals (page 4 of 15) Pin or Name Ball No. E1 GPO_A4 E2 VSSIO_33 E3 VSSIO_33 E4 Int E5 Res E6 Res E7 VSMINUS E8 VSMINUS E9 PD2 E10 PD6 E11 PCS E12 VDD_12 E13 PINT E14 ...
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Table 1 I/O Signals (page 5 of 15) Pin or Name Ball No. F4 Int F5 Int F6 Int F7 Res F8 PD0 F9 PD4 F10 VDD_12 F11 PWE F12 PA3 F13 Res F14 RSTO F15 TMS_D G1 VSSA G2 ...
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Table 1 I/O Signals (page 6 of 15) Pin or Name Ball No. G6 Int G7 Int G8 PD1 G9 VDD_33 G10 VDD_33 G11 Int G12 TDO_D G13 TRST G14 TCK G15 TDI_D H1 TEST_P H2 TEST_N H3 VSSPLL H4 ...
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Table 1 I/O Signals (page 7 of 15) Pin or Name Ball No. H8 Int H9 VSS_12 H10 VSS_12 H11 PCM_RCLK H12 PCM_RSIG H13 PCM_RDATA I H14 PCM_RSYNC I H15 SCSEL J1 TX_P J2 TX_N J3 VDDT J4 VSSD J5 ...
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Table 1 I/O Signals (page 8 of 15) Pin or Name Ball No. J8 Int J9 UTIRXA4 J10 VSS_12 J11 VSS_12 J12 PCM_TSIG J13 PCM_TDATA O J14 PCM_TSYNC O J15 Res K1 VSSA K2 VDDA K3 VSST K4 CLK_IN K5 ...
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Table 1 I/O Signals (page 9 of 15) Pin or Name Ball No. K10 UTITXA4 K11 UTITXA3 K12 UTITXA2 K13 UTITXA0 K14 EOC_REN K15 UTITXA1 L1 RXB_N L2 RXA_N L3 TMS_A L4 VDDPLL L5 CLK_MODE L6 VDDD L7 Int L8 ...
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Table 1 I/O Signals (page 10 of 15) Pin or Name Ball No. L11 UTOSOC L12 UTIRXA3 L13 UTIRXA1 L14 UTIRXA0 L15 MDIO M1 RXA_P M2 RXB_P M3 TDO_A M4 VSSIO_33 M5 Int M6 VDDD M7 Int M8 VDD_12 M9 ...
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Table 1 I/O Signals (page 11 of 15) Pin or Name Ball No. M12 ETHCTLO TXEN RXDV RXSYNC M13 ETHOD2 TXD2 RXD2 M14 ETHOD1 TXD1 RXD1 M15 VSS_12 N1 VSSR N2 VDDR N3 SCAN_MOD E N4 Int N5 Int N6 ...
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Table 1 I/O Signals (page 12 of 15) Pin or Name Ball No. N9 UTID6 RXSYNC_EN I N10 CRSI CRS N11 MDCI MDC N12 MDCO RXCLK MDC N13 UTOD7 N14 CRSO CRS N15 ETHOD3 TXD3 RXD3 P1 HRST_A P2 TDI_A ...
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Table 1 I/O Signals (page 13 of 15) Pin or Name Ball No. P7 Int P8 Int P9 EOC_RCLK P10 ECLK2 PHYCLK P11 ETHID2 RXD2 TXD2 P12 ECLK1 TXCLK RXCLK REFCLK RXCLKREF P13 ETHCTLI RXDV TXEN TXSYNC P14 UTOD6 P15 ...
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Table 1 I/O Signals (page 14 of 15) Pin or Name Ball No. R2 WAKEUP_A R3 XTAL1 R4 Int R5 EEPROM_EN - R6 Int R7 NTR R8 EOC_TCLK R9 EOC_TDATA I R10 EOC_RDATA O R11 COLI COL Preliminary Data Sheet ...
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Table 1 I/O Signals (page 15 of 15) Pin or Name Ball No. R12 ETHID0 RXD0 TXD0 TX R13 ECLK3 RXCLK TXCLK R14 VSS_12 R15 Res 1) Pins that control configuration during hard reset must be pulled up or pushed ...
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General Purpose Pins Table 2 Lists all general purpose pins. Table 2 General Purpose Signals Pin or Name Ball No. K4 CLK_IN L5 CLK_MODE P4 CLKOUT P1 HRST_A C13 HRST_D F14 RSTO R2 WAKE-UP_A AO E15 WAKEUP_D I R3 ...
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Analog Interface Pins Table 3 lists all analog interface pins. Table 3 Analog Interface Pins Pin or Ball Name No. A7 OUT2 A8 INN2 A9 INP2 D5 OUT1 D6 INN1 D7 INP1 J1 TX_P J2 TX_N L1 RXB_N L2 ...
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Table 4 EOC and PCM Pins (page Pin or Name Ball No. P9 EOC_RCLK R10 EOC_RDATA O K14 EOC_REN R8 EOC_TCLK R9 EOC_TDATA I D15 EOC_TEN R7 NTR H11 PCM_RCLK H13 PCM_RDATA I H12 PCM_RSIG H14 PCM_RSYN ...
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Table 4 EOC and PCM Pins (page Pin or Name Ball No. J12 PCM_TSIG J14 PCM_TSYNC O 1) Pins that control configuration during hard reset must be pulled up or pushed down with resistors, as required. See ...
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Table 5 Ethernet or Pins (page Pin or Name Pin Ball Type No. N12 MDCO O M12 ETHCTLO O N13 UTOD7 O P14 UTOD6 O N14 CRSO O P15 COLO O L9 ETHOD0 O M14 ETHOD1 O ...
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Parallel Port Pins Table 6 describes the pins of the parallel port. Table 6 Parallel Port Pins Pin Name Pin Type E13 PINT O C12 PA0 I D13:D12 PA1:PA2 I F12 PA3 I D11 POE I F11 PWE I ...
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UART Pins Table 7 describes pins that connect to the UART line. Table 7 UART Host and Parallel Port Pins Pin Name Pin Type E14 URTRX I D14 URTTX O 2.3.7 EEPROM Pins Table 8 describes pins that enable ...
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Table 9 JTAG Pins (page Pin Name Pin Type G12 TDO_D O L3 TMS_A AI F15 TMS_D I G13 TRST I 1) Pull Up (PU) buffers are 550 K Table 10 Test Pins Pin Name Pin Type ...
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Table 11 Voltage Supply Pins (page Pin H6, J5, J6, K6, L6, M6 C2, C3, G4 D8, E7, E8 A4, A5, A6 Table 12 Ground Pins (page Pin H9, H10, ...
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Table 12 Ground Pins (page Pin 2.4 Pin and Signal Assignment in Different Modes The name of the signal using a multiplexed pin depends on the mode of operation. The pin lists in this ...
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MII Modes Table 13 lists the MII MAC mode pins while Table 13 MII MAC Mode Pins Signal Name Pin Name COL COLI CRS CRSI RXCLK ECLK3 RXD0 ETHID0 RXD1 ETHID1 RXD2 ETHID2 RXD3 ETHID3 RXDV ETHCTLI TXCLK ECLK1 ...
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Table 14 MII PHY Mode Pins (page Signal Name Pin Name RXD0 ETHOD0 RXD1 ETHOD1 RXD2 ETHOD2 RXD3 ETHOD3 RXDV ETHCTLO TXCLK ECLK3 TXD0 ETHID0 TXD1 ETHID1 TXD2 ETHID2 TXD3 ETHID3 TXEN ETHCTLI 1) Pins that control ...
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Table 15 RMII MAC Mode Pins (page Signal Name Pin Name TXD1 ETHOD1 TXEN ETHCTLO 1) Pins that control configuration during hard reset must be pulled up or pushed down with resistors, as required. See “Configuration Pins ...
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Table 17 Typical SMII Mode Pins Signal Name Pin Name RX ETHOD0 TX ETHID0 REFCLK ECLK1 TXSYNC ETHCTLI 1) Pins that control configuration during hard reset must be pulled up or pushed down with resistors, as required. See “Configuration Pins ...
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I Table 19 Serial Management Interface (SMI) Pins for MAC Modes Signal Name Pin Name MDCO MDCO MDIO MDIO Table 20 Serial Management Interface (SMI) Pins for PHY Modes Signal Name Pin Name MDCI MDCI MDIO MDIO Preliminary Data Sheet ...
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Functional Overview This section outlines the functional description of the components in the PEF 22827 and provides information on the JTAG Interface. 3.1 Digital Block - Functional Overview The digital transceiver performs digital functions for the VDSL modem. These ...
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Figure 4 PEF 22827 Functional Block Diagram Preliminary Data Sheet Functional Overview 56 VDSL6100i PEF 22827 vdsl6100i_block Rev. 1.1, 2005-01-30 ...
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JTAG Interface The test logic consists of a boundary scan register and other building blocks, and is accessed through a Test Access Port (TAP). The TAP includes the TCK, TMS_A, TMS_D, TDI_A, TDI_D, TDO_A and TDO_D pins. The Test ...
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Functional Description – Digital Block The digital transceiver performs digital functions for the VDSL modem. These functions have been listed below according to the blocks contained in the main functional block diagram (see figure 5): • Physical Medium Dependent ...
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TPS-TC and Ethernet Network Interface EOC MII TPS- Interface and Rx (HDLC ) Buffers IC Peripheral Control 16 KBytes 24 KBytes ROM RAM Serial Interface Internal Microcontroller UART Figure 5 VDSL Digital Transceiver Functional Block Diagram Preliminary Data ...
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The detailed functional description of the digital transceiver is organized as shown below: • “Firmware” on Page 60 • “Physical Media Dependent (PMD) Layer” on Page 60 • “Physical Medium Specific Transmission Convergence (PMS-TC) Layer” on Page 62 • “Ethernet ...
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Notch filter registers insert a notch into the transmission frequency band. This prevents interference with other systems (amateur radio) that use narrow band transmission in the VDSL frequency band. Table 21 registers for 38.88 MHz for different ham radio bands, ...
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QAM Demodulator (Receiver) The QAM demodulator receives a sampled signal from the ADC in the analog block, demodulates the QAM symbols from the two modulated carriers and delivers the two bit streams to the TC layer. The incoming signal ...
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Interleaving • Construction of a Transmission Frame • Splitting the Transmission Frame into PMD Frames 4.4.1.1 Scrambling Before Reed Solomon (RS) encoding, a self-synchronizing algorithm scrambles (randomizes) the frame header (without the SYNC word), the payload on the fast ...
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Reed Solomon code at the output of the interleaver. For all settings, must be a multiple of the interleaver block length ( M is any integer from 0 through 64. M • = The interleaving depth index. there ...
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Header: 5 Bytes SYNC Control Fast Word Word Channel 2 Bytes 3 Bytes PF Bytes Fast (F) Bytes Figure 6 Transmission Frame Format The payload of each transmission frame includes two fast channel fields and two slow channel fields, which ...
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Table 24 Transmission Frame Header Byte Name Description 2 Control 1 Control and management information, word 1. 3 Control 2 Control and management information, word 2. 4 Control 3 Control and management information, word 3. The four CRC bits (CRC_1 ...
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One Splitting Cycle = (N PMD Frame 1 for Carrier 1 (405 Bytes) SYNC Word Bytes Cycle 1, Input Frame 1 SYNC Word Bytes SYNC Word ...
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PRESYNC - In this state, the receiver verifies the match of bits in the SYNC word found during the HUNT and searches for a second consecutive match. If two consecutive matches are found, the state switches from PRESYNC to ...
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Reed Solomon Decoding Reed Solomon code words are decoded for both fast and slow streams. For more information on Reed Solomon code words, see Page 63. 4.4.2.4 Unscrambling After Reed Solomon (RS) decoding, a self-synchronizing algorithm unscrambles the header, ...
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Table 25 HDLC Frame Contents Contents Description 7E Opening Flag Sequence H FF Address Field H 03 Control Field H Data Information Field FCS-1 First byte of HDLC_FCS FCS-2 Second byte of HDLC_FCS 7E Closing flag sequence H Data is ...
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MII Interface and Configuration When configured as an Ethernet MAC, the digital transceiver can be connected to an Ethernet PHY through MII or RMII interfaces. In this case, the Serial Management Interface (SMI) provides access to the attached Ethernet ...
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Management and Control In the digital transceiver, management and control are implemented by the following: • Internal micro controller • Management interfaces • Configuration pins • EEPROM • JTAG 4.6.1 Internal Micro Controller An 8-bit internal micro controller is ...
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Configuration Pins Several pins function as configuration pins in addition to their normal tasks. After power is turned ON, and before these pins assume their normal function, the value of the pins is sampled to determine the configuration. Make ...
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Functional Description – Analog Block The Analog Block of the PEF 22827 provides a filterless VDSL AFE (Analog Front 1) End) , which is programmable under system control and modifiable through management commands. The AFE is connected to the ...
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Filterless AFE 1) The filterless AFE has no transmission and reception filters. Echo noise is eliminated by connecting to an External Adaptive Hybrid that automatically matches any line impedance and efficiently removes echo noise. 5.3 Functional Block Diagram – ...
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DAC DAC 13 Bits Analog Block ADC ADC 12 Bits Controller Interface AFE Controller Figure 9 Functional Block Diagram - Analog Block 5.4 Filter Tuning Unit PEF 22827 has a built-in filter tuning unit tuning. The filter mode depends on ...
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The digital block controls filter tuning in the AFE with the WAK_PLL_TUN_RF (0D The tuning cycle for pre-filter and post-filter parameter adjustment is set by the digital block software transition of TUNE_START tuning cycle. The filter ...
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Post Tuning Filter (POFI) The Post Tuning Filter (POFI third order Chebyshev filter with a programmable corner frequency. See “Corner Frequency and Tuning” on Page 261 description about programming the corner frequency. No external filter is required. ...
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Clock Generation When the VDSL system operates in LT Mode (master mode), either the internal crystal (DCXO external clock can generate the master clock external clock is used to generate the master clock, the external ...
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Functional Description – Line Driver Block This section shows the block diagram of the internal line driver and describes Power Down mode. 6.1 Functional Block Diagram – Line Driver The functional block diagram of line driver, located in the ...
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Operation – Digital Block This chapter describes the digital block operations. The operations of the analog block are controlled in the digital block. Line driver block operations are described in “Operation – Line Driver” on Page Digital block operations ...
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Table 27 Configuration Pins (page Normal Pin Pin # Name EOC_TDATA R9(MSB) EOC_RCLK P9 EOC_RDATA R10 EOC_REN K14(LSB) NTR R7 COLO P15 ETHOD3: N15, ETHOD0 M13, M14, L9 EE_EN R5 7.2 System Clock A crystal with the ...
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Digtal IC CLKIN Timing Recovery Serial Interface Figure 12 System Clock Generation 7.3 EEPROM A 32-Kbyte or a 64-Kbyte EEPROM is supported. The 32-Kbyte EEPROM can hold one firmware version, with its parameters zone. The 64-Kbyte EEPROM can hold two ...
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EEPROM Signature (55 H 0001 Active FW Bank Number H 0002 FW Bank 1 Signature (11 H 0003 FW Bank 2 Signature (22 H 0004 Reserved ( 0005 Reserved ( 0006 :0007 ...
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FW Bank Signature (0002 unless this field indicates that it is valid. Values of 11 Bank 2) indicate valid banks. • Pointer to FW Bank 1 (0006 bank points to the address where the corresponding firmware bank begins. ...
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DF_STP1 (7880 :789E H F89F :F8BD ) - See H H EEPROM” on page 92. Table 28 Register Parameter Mapping in EEPROM (page Address (Hex) Parameter or Register Name Bank 1 Bank 2 7802 F802 LINK_MODE ...
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Table 28 Register Parameter Mapping in EEPROM (page Address (Hex) Parameter or Register Name Bank 1 Bank 2 781B F81B NTCHA1_L_US1 781C F81C NTCHA2_L_US1 781D F81D NTCHA_H_US1 781E F81E NTCHB_L_US1 781F F81F NTCHB_H_US1 7820 F820 NTCHA1_L_DS2 7821 ...
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Table 28 Register Parameter Mapping in EEPROM (page Address (Hex) Parameter or Register Name Bank 1 Bank 2 7826 F826 NTCHA2_L_US2 7827 F827 NTCHA_H_US2 7828 F828 NTCHB_L_US2 7829 F829 NTCHB_H_US2 7AD0 FAD0 PBO_K 7AD1 FAD1 PBO_US1D 7AD2 ...
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Table 28 Register Parameter Mapping in EEPROM (page Address (Hex) Parameter or Register Name Bank 1 Bank 2 7AED: FAED: RA_CF_U2 7AEE FAEE 7AEF FAEF RA_SR_D1 7AF0 FAF0 RA_SR_D2 7AF1 FAF1 RA_SR_U1 7AF2 FAF2 RA_SR_U2 7AF3 FAF3 ...
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Table 29 WS_STP Parameter Mapping in EEPROM (page Address (Hex) Parameter Bank 1 Bank 2 786A F86A CONSTELATION_DS2 This value is a power define the 786B F86B CONSTELATION_US1 This value is a power of ...
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Table 29 WS_STP Parameter Mapping in EEPROM (page Address (Hex) Parameter Bank 1 Bank 2 7879 F879 INTERLEAVER_I 787A F87A FAST_SIZE_DS 787B F87B FAST_SIZE_US 787C F87C FFEC_SIZE_LT 787D F87D FFEC_SIZE_NT 787E F87E SFEC_SIZE_LT 787F F87F SFEC_SIZE_NT Preliminary ...
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In Table 29, (1) indicates the parameter zone for Firmware Bank 1 and (2) indicates the parameter zone for Firmware Bank 2. Table 30 DF_STP1 and DF_STP2 Parameter Mapping in EEPROM (page Address (Hex) Parameter DF_STP1 ...
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Table 30 DF_STP1 and DF_STP2 Parameter Mapping in EEPROM (page Address (Hex) Parameter DF_STP1 DF_STP2 7890 (1) 78AF (1) PSD_LEVEL_DS1 H H F890 (2) F8AF ( 7891 (1) 78B0 (1) PSD_LEVEL_DS2 H H F891 ...
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Table 30 DF_STP1 and DF_STP2 Parameter Mapping in EEPROM (page Address (Hex) Parameter DF_STP1 DF_STP2 789B (1) 78BA (1) FFEC_SIZE_LT H H 789B (2) 78BA ( 789C (1) 78BB (1) FFEC_SIZE_NT H H 789C ...
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Table 31 DF_STP1 Parameter Values in EEPROM Parameter CENTER_FREQ_DS1 CENTER_FREQ_DS2 CENTER_FREQ_US1 CENTER_FREQ_US2 CONSTELATION_DS1 CONSTELATION_DS2 CONSTELATION_US1 CONSTELATION_US2 SYMBOL_RATE_DS1 SYMBOL_RATE_DS2 SYMBOL_RATE_US1 SYMBOL_RATE_US2 PSD_LEVEL_DS1 PSD_LEVEL_DS2 PSD_LEVEL_US1 PSD_LEVEL_US2 PSD_MASK INTERLEAVER_M_DS INTERLEAVER_M_US INTERLEAVER_I FAST_SIZE_DS FAST_SIZE_US FFEC_SIZE_LT FFEC_SIZE_NT SFEC_SIZE_LT SFEC_SIZE_NT Table 32 provides the values of ...
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Table 32 DF_STP2 Parameter Values in EEPROM Parameter CENTER_FREQ_DS1 CENTER_FREQ_DS2 CENTER_FREQ_US1 CENTER_FREQ_US2 CONSTELATION_DS1 CONSTELATION_DS2 CONSTELATION_US1 CONSTELATION_US2 SYMBOL_RATE_DS1 SYMBOL_RATE_DS2 SYMBOL_RATE_US1 SYMBOL_RATE_US2 PSD_LEVEL_DS1 PSD_LEVEL_DS2 PSD_LEVEL_US1 PSD_LEVEL_US2 PSD_MASK INTERLEAVER_M_DS INTERLEAVER_M_US INTERLEAVER_I FAST_SIZE_DS FAST_SIZE_US FFEC_SIZE_LT FFEC_SIZE_NT SFEC_SIZE_LT SFEC_SIZE_NT 7.3.1.4 Spare Zones Spare zones are ...
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Accessing EEPROM Access EEPROM for read and write operations through a set of user registers. After firmware is loaded to EEPROM, if the write protect pin of the EEPROM is connected correctly to the digital transceiver, the EEPROM is ...
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Internal RAM Management The internal micro controller is connected to an internal 24-Kbyte RAM, which holds both code and data. This RAM is mapped to addresses 2000 stored in the following addresses: • 2000 :5AFF H H • 6000 ...
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Firmware Download from EEPROM Firmware download takes up to three seconds. After it is finishes, the digital transceiver does one of the following: • If firmware download was successful, normal operation begins. • If firmware download is not successful, ...
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After download ends, start normal operation by setting the FW_DLOAD register at 5F6F verify the checksum of the code before starting normal operation mode, see H “Internal RAM Management” on Page 7.6 Application Management As soon ...
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Management of Standard Compliant Links Link management is performed in two layers, LT and NT, as shown in LT External Host LT Link Management LT Link State Machine PM Controls Figure 14 Link Management at the LT and the ...
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Power OFF (Service Installation or Change) Power Up Request No (Quiet) Cold Start (Time out = T1) Sync Loss in Idle Yes Steady State Transmission Idle Request Idle Figure 15 VDSL Transmission Profile Link State Machine The Link State Machine ...
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S6: SYNC_LOSS x_ACQUIRE LOS, LOF S7: TRIGGER x_TRIG New STP Confirmed New CR_STP and r_trig Set Detected S5: ACTIVE x_DATA Figure 16 The Link State Machine The LT link management layer controls and configures the Link State Machine and establishes ...
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Configuration of Standard Compliant Links Fields in the MAIN_CTL, MAIN_MODE and LINK_MODE registers control and configure links. For more information on these fields, see detailed descriptions in: • “MAIN_CTL” on Page 186 • “MAIN_MODE” on Page 186 • “LINK_MODE” ...
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Table 35 shows the address to read for each parameter in the customizable default STPs. 7.6.4.1 Modifying STPs A target STP is the set of transmission parameters that describes the requested link. The following registers enable access to target STP ...
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Table 34 Current and Warm Start STP Mapping (page Address (Hex) Parameter CR_STP WS_STP 5E11 5E30 CENTER_FREQ_DS1 5E13 5E32 CENTER_FREQ_DS2 5E15 5E34 CENTER_FREQ_US1 5E17 5E36 CENTER_FREQ_US2 5E19 5E38 CONSTELATION_DS1 This value is a power ...
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Table 34 Current and Warm Start STP Mapping (page Address (Hex) Parameter CR_STP WS_STP 5E23 5E42 PSD_LEVEL_US1 5E24 5E43 PSD_LEVEL_US2 5E25 5E44 PSD_MASK 5E26 5E45 Reserved 5E27 5E46 INTERLEAVER_M_DS Range 0:64 Interleaver OFF. 5E28 5E47 ...
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Table 34 Current and Warm Start STP Mapping (page Address (Hex) Parameter CR_STP WS_STP 5E2D 5E4C FFEC_SIZE_NT 5E2E 5E4D SFEC_SIZE_LT 5E2F 5E4E SFEC_SIZE_NT Table 35 Default STP Mapping (page Address (Hex) Parameter DF_STP1 DF_STP2 ...
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Table 35 Default STP Mapping (page Address (Hex) Parameter DF_STP1 DF_STP2 5ECF 5EEE CENTER_FREQ_US1 5ED1 5EF0 CENTER_FREQ_US2 5ED3 5EF2 CONSTELATION_DS1 This value is a power define the 5ED4 5EF3 CONSTELATION_DS2 This value is a ...
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Table 35 Default STP Mapping (page Address (Hex) Parameter DF_STP1 DF_STP2 5EDF 5EFE PSD_MASK 5EE0 5EFF Reserved 5EE1 5F00 INTERLEAVER_M_DS Range 0:64 Interleaver OFF. 5EE2 5F01 INTERLEAVER_M_US Range 0:64 Interleaver OFF. 5EE3 5F02 ...
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Table 35 Default STP Mapping (page Address (Hex) Parameter DF_STP1 DF_STP2 5EE7 5F06 FFEC_SIZE_NT 5EE8 5F07 SFEC_SIZE_LT 5EE9 5F08 SFEC_SIZE_NT 7.6.4.4 Setting the Gross Bit Rate Upstream and downstream gross bit rates (bits in the air) are ...
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Note: If this relation is not maintained, the target link is not established. The default link is established instead, and the PROFILE_ERR bit in the GEN_STATUS2 register (8F10 ) is asserted. H 7.6.4.5 Net Throughput The structure of the transmission ...
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Setting the Interleaver The interleaver is configured by setting the (see Table 68 “Link Control” on Page I • is the interleaver block length. Supported values are M • is the interleaver depth index. The following interleaver characteristics are ...
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Table 37 shows how to calculate protection provided by the interleaver for 21.6 Mbit/s downstream operation, with Table 37 Protection Calculation Parameters, 21.6 Bit Rate, DS, S/4 Parameter F Fast Channel Bytes ( ), must be a multiple of 4 ...
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Table 38 Protection Calculation Parameters, 9.99 Bit Rate, Upstream, S/8 (page Parameter E Erased Bytes ( ) B E Protection Time Upstream memory allocation plus downstream memory allocation may not exceed 24 KB. ...
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The line attenuation can be modeled after the ETSI recommendation as follows according to the formula where: • A= Attenuation in dB • K= Wire type constant as measured by [ (Hz) • ...
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Write the opcode of the parameter to the VOC_OC register. For detailed descriptions of opcodes and related data fields see on Page 193 necessary, in VOC_DAT, write the number of the band (CARRIER_NUM) to read. All other ...
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RA STATE Achieving the optimal link Monitoring the optimal link Figure 18 RA Simplified Flow Diagram Achieving the Optimal Link In this state, the RA algorithm takes the following parameters into account: • Modem limitations • Noise profile including self ...
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Computes a raw estimate of the received SNR for each band. 4. Loads a reduced profile to measure the actual SNR. 5. Sets the optimal profile based on the actual SNR and the following parameters: – Minimum margin – ...
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Yes Automatic RA rerun Yes Automatic RA rerun Set rerun recommendation Figure 19 RA Monitor Flow Diagram Preliminary Data Sheet Achieving the optimal link Monitor was selected Wait 1 second 1 Second Passed Link mode != Warm link ? No ...
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Configuring the RA Process The following registers are required for configuring the Rate Adaptive (RA) process: • Noise margin registers (LT only) – RA_MN_MRG_D1 – RA_MN_MRG_D2 – RA_MN_MRG_U0 – RA_MN_MRG_U1 – RA_MN_MRG_U2 • Maximum bit rate registers (LT only) ...
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F LOW_BAND2 LOW_BAND1 If Long Range is enabled, the RA process may automatically choose to use US0 (0.25- 0.138). 7.6.7.6 Running the RA Process with PBO in Changing Conditions The Power Back Off (PBO) mechanism computes ...
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To implement Long Reach VDSL without running the RA process, see, Long Reach VDSL Manually” on Page 7.6.8 Implementing Long Reach VDSL Manually LR-VDSL operation mode operates only on one upstream band. On this band, only the constellation can be ...
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To write a byte to the remote NT, do the following at the LT: 1. Write the address of the remote register to which to write, into the VOC_DAT register. 2. Write 94 to the VOC_OC register. For detailed descriptions ...
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MII Configuration for a PHY-MAC Scenario In a PHY-MAC scenario, the SMI registers of the remote 10/100Base-TX PHY are not changed by the remote MAC. Local SMI registers are not affected by the remote 10/ 100Base-TX PHY. Table 40 ...
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Table 40 SMI Register Behavior (page SMI Register and Behavior Address (Hex) 12 (RSLTR) Result Register - Data from last read operation. In the remote side, MII configuration for speed and duplex parameters in the digital transceiver ...
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If the ANEGEN bit (bit 12) is cleared, these parameters are derived from the SPEED (bit 13) and DUPLEX (bit 8) bits in the BMCR register of the attached PHY. 7.6.10.1.3 MII Configuration for a PHY-PHY Scenario Figure 21 ...
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The Ethernet interface stops applying back pressure when the free space in the reception buffer reaches the appropriate threshold. The Ethernet interface starts generating back pressure after a legal inter-packet gap (IPG). If there are packets to transmit, they ...
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Adjustable Back Off Algorithm Ethernet transmitter activity is increased by resetting the collision counter for a packet after less than the standard 16 retries. This resets the exponential back off algorithm, thereby allowing insertion of shorter IPGs than are possible ...
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The micro controller can read entries in the address table. It reads the source address through a protocol and an address counter points to an entry in the table. The counter is incremented on each read and ...
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Local Loop Back Figure 22 Remote Loop Back and Local Loop Back 7.6.11 The Dying Gasp Mechanism To monitor voltage drops in the DSLAM at the NT end, do the following: 1. Connect the external voltage drop ...
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Operation – Line Driver This section describes the following: • Calculating Line Driver Gain in a VDSL Application 8.1 Calculating Line Driver Gain in a VDSL Application To achieve typical power of 10 dBm for VDSL on the line, ...
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A crest factor (CF) of 3.5 for single carrier VDSL must also be considered. Calculate peak-to-peak voltage V L,p-p power as follows – – The gain of the line driver circuitry ...
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Interfaces This chapter describes the following interfaces: • JTAG Interface (Boundary Scan) • “Management Interfaces” on Page 135 • “Network Interfaces” on Page 156 • “EOC Interface” on Page 167 2 • “I C Interface for EEPROM” on Page ...
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To select a test mode, serially load one of the 3-bit instruction codes shown in into the JTAG instruction register via the TDI (TDI_D or TDI_A) pin, least significant byte first. Table 42 Boundary Scan Test Mode Selection 3-bit Instruction ...
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For the WR, OR and ND opcodes the parameter is the data used for the operation. For example: To write 8C0B A4 <Enter> • The parameter is optional for the RD opcode. If used, it specifies ...
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For detailed timing diagrams of read and write cycles, see Host Interface” on Page Table 44 Parallel Port Signals Name Input/Output PA3:PA0 Input PD7:PD0 Input/Output PCS Input PWE Input POE Input PINT Output PA[3:0] PCS POE PD[7:0] Figure ...
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Parallel Port Registers Table 45 shows the memory mapping of the parallel port registers and indicates the page on which its detailed description begins. Table 45 Parallel Port Registers Address (Hex) Short Name Long Name 00 CMD 01 CNT ...
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Byte Counter Register (CNT) The byte counter (CNT) register contains the number of bytes to be transferred to or from the parallel port. The content of CNT Byte Counter Register 7 6 Field Bits Type Description BYTE_COUNT 7:0 rw Address ...
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Field Bits Type Description DATA_WORD 31:0 rw Interrupt Request Register (INTR) The INTR register indicates the cause of an interrupt on the PINT signal. This register can also be polled while the interrupt is masked by the MASK register (09 ...
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Field Bits Type Description Res 7:4 rw ERROR_MASK 3 rw READY_MASK 2 rw Res 1:0 rw Host Interface ID (HIID) The HIID register specifies the ID of the parallel port (host interface). HIID Host Interface Field Bits ...
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Write Cycle To execute a single write cycle, the host should first verify that the CMD register ( cleared to 0. Next the host should set the 16-bit ADDR register (at 02 internal address and load up ...
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Table 46 SMI Signals in MAC Interface Mode Signal Direction Function MDCO OUT MII Serial Management Data Clock generated digital transceiver when it is configured as a MAC device. • • • MDIO IN/OUT MII Serial Management Data Input/Output • ...
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Preamble - A string of at least 32 consecutive ones (1) on MDIO, optional. • SFD - Start of Frame Delimiter. • Opcode. • PHY Address - Defined by configuration pins as described in During Hard Reset” ...
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Table 49 Serial Management Interface (SMI) Registers (PHY Mode) (page SMI Address Mnemonic 12 RSLTR 9.2.3.3 Accessing Internal Memory Space through the SMI The Serial Management Interface (SMI) uses three 16-bit proprietary ...
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Table 50 Serial Management Interface (SMI) Registers (MAC Mode) SMI Address Mnemonic Register Description 00 BMCR H 01 BMSR H 02 :03 OUI ANAR H 05 ANLPAR H 9.2.4 Detailed Description of SMI Registers This section describes ...
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Field Bits Type Description LPBK 14 SPEED 13 ANEGEN 12 Res 11 ISOLATE 10 RESANEG 9 DUPLEX 8 COL 7 Res 6:1 RESET_DIS 0 ABLE Basic Mode Status Register (BMSR) The 16-bit BMSR register contains the status of basic operation ...
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BMSR Basic Mode Status Register 15 14 Res 100F 100H ANEG_ Res MFPS STATUS r r Field Bits Type Description Res 15 r 100F 14 r 100H 13 r 10F 12 r 10H 11 r Res ...
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Field Bits Type Description REMOTE_ER ANEGABILITY 3 r LINK_STATUS 2 r JABBER 1 r EXTEND 0 r Organizationally Unique Identifier (OUI) Register (OUI) This 32-bit PHY identifier register holds a unique identifier for the digital transceiver consisting ...
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Field Bits Type Description OUI3:OUI24 31:10 r VNDR_MDL 9:4 r MDL_REV 3:0 r Automatic Negotiation Advertisement Register (ANAR) The 16-bit automatic negotiation advertisement register (ANAR) controls announcement of the flow control ability and Carrier Sense Multiple Access-Collision Detected (CSMA- CD) ...
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Field Bits Type Description 100HD 7 rw 10FD 6 rw 10HD 5 rw SELECTOR 4:0 rw Automatic Negotiation Link Partner Advertisement Register (ANLPAR) The 16-bit automatic negotiation link partner advertisement register (ANLPAR) controls announcement of the flow control ability and ...
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Field Bits Type Description Res 9 rw 100FD 8 rw 100HD 7 rw 10FD 6 rw 10HD 5 rw SELECTOR 4:0 rw Internal Address Space Register (IADDSR) The external host writes to the 16-bit that the next read or write ...
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OPCDR Opcode Register BUSY rw Field Bits Type Description WRITE_DATA 15:8 rw BUSY 7 rw Res 6:2 rw READ_OP 1 rw WRITE_OP 0 rw Result Register (RSLTR) Bits 15:8 of the 16-bit result register contains the ...
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RSLTR Result Register Field Bits Type Description Res 15:8 rw READ_DATA 7:0 rw Status of Proprietary Information Register (SPR_PTR) This 16-bit register contains information about where to find the actual speed and duplex parameters in the ...
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Field Bits Type Description DLOC 7:4 rw SLOC 3:0 rw Status of Proprietary Information Register (SPR) This 16-bit register contains the status of proprietary information. SPR Status of Proprietary Information Register(14 ...
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Field Bits Type Description VLINK 13 VFAIL 12 rw Res 11 rw CHKDONE 10:9 rw Res RMAC 5 rw Res 4:0 rw 9.3 Network Interfaces Network interfaces serve as the main data ...
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VDSL link using the AFE, and the local Ethernet link using an Ethernet PHY. This MII interface is compatible with the IEEE 802.3 standard. Figure 26 shows the block diagram when the digital transceiver is configured as ...
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VDSL Digital Transceiver as a MAC Figure 27 Signals for a MAC Configuration with MII Interface to a PHY 9.3.1.2 PHY Configuration with MII Interface Configuration as a PHY uses a Media Independent Interface (MII) to interface to a MAC ...
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VDSL AFE VDSL Link Figure 28 Block Diagram of PHY Configuration with MII Interface to a MAC Figure 29 shows the names of the signals used for the MII interface between the PHY and the MAC, with the corresponding MII ...
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VDSL Digital Transceiver as a PHY PHYCLK Figure 29 Signals for PHY Configuration with MII Interface to a MAC x 9.3.2 MII Interfaces This section describes the different kinds of Media Independent Interface (MII) supported. 9.3.2.1 MII Interface to a ...
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Figure 30 shows the block diagram when the digital transceiver is configured as a MAC and uses MII to interface to a PHY unit. VDSL AFE VDSL Link Figure 30 Block Diagram of MAC Configuration with MII Interface to a ...
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VDSL Digital Transceiver as a MAC Figure 31 Signals for MAC Configuration with MII Interface to a PHY 9.3.2.2 MII Interface to a MAC in a PHY Configuration A digital transceiver configured as a PHY that uses a Media Independent ...
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Figure 33 shows the names of the pins (in parentheses) used for the MII interface between the PHY and the MAC, with the corresponding MII signal and the direction for each. It also shows the external 25 MHz source clock ...
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The block diagram of the digital transceiver when it is configured as a MAC and uses RMII to interface to a PHY is the same as for MII, as shown in MAC Configuration with MII Interface to a PHY, on ...
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Figure 35 shows the names of the pins (in parentheses) used for the RMII interface between the PHY and the MAC, with the corresponding RMII signal and the direction for each. It also shows the external 50 MHz source clock ...
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Figure 36 shows the names of the pins (in parentheses) used for a typical SMII interface between the PHY and the MAC, with the corresponding SMII signal and the direction for each. It also shows the external 125 MHz source ...
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Figure 37 shows the names of the pins (in parentheses) used for the source synchronous SMII interface between the PHY and the MAC, with the corresponding source synchronous SMII signal and the direction for each. It also shows the external ...
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EOC_TEN EOC_TDATA EOC_TCLK EOC_REN EOC_RDATA EOC_RCLK Figure 38 EOC Interface Signals Table 51 EOC Signals Signal I/O EOC_TDATA I EOC_RDATA O EOC_TCLK I EOC_RCLK I EOC_TEN O EOC_REN O 1) The maximum clock frequency of the EOC_TCLK and EOC_RCLK signals ...
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EOC_TCLK EOC_TDATA EOC_TEN EOC_RCLK EOC_RDATA valid EOC_REN Figure 39 EOC Signals Timing Diagram 2 9 Interface for EEPROM Connection to the EEPROM is implemented with a standard I I2CCLK and I2CD pins. The internal 8051 microprocessor emulates the ...
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Control Byte Figure Read or Write Transaction The control byte identifies the slave IC, which ...
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Memory and Register Descriptions – Digital Block This section describes the registers that are dedicated to digital operations. The overview includes lists of the registers with their offset addresses. Detailed descriptions of each follow, beginning on 10.1 Register Overview ...
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Table 52 Register List (page Offset Short Name Address 8D3F L_FR_LOS_CNT H 7F11 SNR_BER H 7F18 SNR_MAX H 7F19 SNR_MIN H STPs 5E11 :5 CR_STP H E2F H 5E30 :5 WS_STP H E4E H 5ECB : DF_STP1 ...
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Table 52 Register List (page Offset Short Name Address 5DCC NTCHA1_L (US2) H 5DCD NTCHA2_L (US2) H 5DCE NTCHA_H (US2) H 5DCF NTCHB_L (US2) H 5DD0 NTCHB_H (US2) H Version Status Registers 5F62 HW_VER_FIELD H 5F63 ROM_VER_FIELD ...
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Table 52 Register List (page Offset Short Name Address 8C60 ADC H 8C62 DAC H 8C63 PREFI_POFI H 8C64 ACE_MBUF_AGC H 8C65 POCO 8C66 AGC 8C67 ALOOP_BIAS 8C68 DCXO 8C6C FC_TUNE 8C6D WAK_PLL_TUN_RF 8C6F XTAL_TUN_PAR 8C72 PLL_PAR ...
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Table 52 Register List (page Offset Short Name Address 8CE8 MII_SFTL H 8CE9 MII_SFCS H 8CEA MII_SOTO H 8CEB MII_SORO H 8CEC MII_BCAST H 8CED RXPAUS H 8CEE TXPAUS H 8CEF TXBCNT H 8CF0 RXBCNT H 8CF3 ...
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Table 52 Register List (page Offset Short Name Address 5B04 PBO_MINPSD H Rate Adaptive Process Registers 5B10 RA_COMMAND H 5B11 RA_MN_MRG_D1 H 5B12 RA_MN_MRG_D2 H 5B13 RA_MN_MRG_U1 H 5B14 RA_MN_MRG_U2 H 5B19 :5 RA_MX_RATE_DS H B1A H ...
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Table 52 Register List (page Offset Short Name Address 5B31 RA_MN_MRG_U0 H 5B32 RA_TLAN_PSD_DS1_MAX H 5B40 RA_STATUS H 5B41 RA_RESTRT_CNT H 5B42 RA_RSLT_D1 H 5B43 RA_RSLT_D2 H 5B44 RA_RSLT_U1 H 5B45 RA_RSLT_U2 H 10.2 Register Lists by ...
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Table 54 Firmware Control Register Offset Address Short Name 5F6F FW_DLOAD H Table 55 EEPROM Control Registers Offset Address Short Name 5F70 :5F71 EEP_ADDR H H 5F72 EEP_LENGTH H 5F73 EEP_CHKSUM H 5F74 :5FF3 EEP_DATA H H 5FF6 EEP_COMMAND H ...
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Table 57 Analog Front End (AFE) Registers (page Offset Address Short Name 8C68 DCXO 8C6C FC_TUNE 8C6D WAK_PLL_TU N_RF 8C6F XTAL_TUN_P AR 8C72 PLL_PAR Table 58 Main Control Registers Offset Address Short Name 8F00 MAIN_CTL H 8F01 ...
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Table 59 Main Status Registers (page Offset Address Short Name 7F11 SNR_BER H 7F18 SNR_MAX H 7F19 SNR_MIN H Table 60 STPs Offset Address Short Name 5E11 :5E2F CR_STP H H 5E30 :5E4E WS_STP H H 5ECB ...
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Table 61 Notch Filter Registers (page Offset Address Short Name 5DCC NTCHA1_L H 5DCD NTCHA2_L H 5DCE NTCHA_H H 5DCF NTCHB_L H 5DD0 NTCHB_H H Table 62 MII Control Registers Offset Address Short Name 8D40 MIICNTL H ...
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Table 65 MII Status Registers Offset Address Short Name 8CE0 MII_SALE H 8CE1 MII_SSCF H 8CE2 MII_SMCF H 8CE3 MII_SDT H 8CE4 MII_SLC H 8CE5 MII_SEC H 8CE6 MII_SRE H 8CE7 MII_SCSE H 8CE8 MII_SFTL H 8CE9 MII_SFCS H 8CEA ...
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Table 67 RA Process Registers (page Offset Address Short Name 5B10 RA_COMMAND H 5B11 RA_MN_MRG_D1 H 5B12 RA_MN_MRG_D2 H 5B13 RA_MN_MRG_U1 H 5B14 RA_MN_MRG_U2 H 5B19 :5B1A RA_MX_RATE_DS H H 5B1B :5B1C RA_MX_RATE_US H H 5B1D :5B1E ...
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Table 67 RA Process Registers (page Offset Address Short Name 5B42 RA_RSLT_D1 H 5B43 RA_RSLT_D2 H 5B44 RA_RSLT_U1 H 5B45 RA_RSLT_U2 H Preliminary Data Sheet Memory and Register Descriptions – Digital Block Long Name D1 Band Use ...
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Detailed Register Descriptions – Digital Block This section contains detailed descriptions of the registers specific to the digital block on the PEF 22827, grouped as follows: • “Main Control Registers” on Page 185 • “Main Status Registers” on Page ...
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MAIN_CTL Main Control Register 7 6 Field Bits Typ e Res 7:2 sc HRST 1 sc SRST 0 sc 10.4.2 Main Operation Mode Register (MAIN_MODE) The MAIN_MODE register defines the conditions for the main operations of the device. MAIN_MODE Main ...
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Field Bits Typ e LB 7:6 rw Res 5:3 rw MAIN_MODE 2:0 rw 10.4.3 Link Operation Mode Register (LINK_MODE) The LINK_MODE register defines conditions for link operation. The reset value is 0100 1000 ( LINK_MODE Link Operation Mode ...
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Field Bits Type Description AH_EN 6 rw DF0_SKIP 5 rw Res 4 rw PBO_EN 3 rw EOC_EN 2 rw ADD_MRGN 1 rw INITIATOR 0 rw 10.4.4 VOC Control Register (VOC_CNTL) The VOC_CNTL register enables access to local and remote parameters ...
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For details and descriptions of opcodes and related data fields see: • “Link Control” on Page • “Link Performance Parameters” on Page • “Access to Remote Registers” on Page VOC_CNTL VOC Control Register 7 6 Field Bits Typ e VOC_CNTL ...
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VOC_OC VOC Message Opcode to Send Register (8F05 7 6 Field Bits Typ e VOC_OC 7:0 rw 10.4.6 VOC Data to Send Register (VOC_DAT) The 16-bit VOC_DATspecifies VDSL overhead channel (VOC) message parameters and the 12 bits of VOC data ...
Page 191
VOC_DAT VOC Data to Send Register Field Bits Typ e STP_CODE 15 CARRIER_DI CARRIER_NU VOC_DATA 11:0 rw Preliminary Data Sheet (8F06 :8F07 ) H H VOC_DATA[15: ...
Page 192
Table 68 Link Control (page Parameter Opcode PROFILE 0010 0000 (Not currently ( supported) INTERLV 0010 0001 ( FRAME 0010 0010 ( PSDMASK 0010 0011 ( PSDLEVEL 0010 ...
Page 193
Table 68 Link Control (page Parameter Opcode CONSTEL 0010 0111 ( CENFREQN 0010 1000 ( • Table 69 Link Performance Parameters Parameter Opcode SNR 0000 0001 ( ATT 0000 0011 (03 ...
Page 194
Table 70 Access to Remote Registers Parameter VOC_OC Opcode REMOTE_RD 1001 0011 ( NEXT_WORD_R 1110 0100 ( REMOTE_WR 1001 0100 ( NEXT_WORD_W 1110 0011 ( REMOTE_WR_BT 0000 0110 ( ...
Page 195
Table 70 Access to Remote Registers Parameter VOC_OC Opcode xxxx REM_16_WR_BT 0010 number of bytes to write. xxxx REM_16_RD_BT 0001 number of bytes to write. 10.4.7 ...
Page 196
Field Bits Type Description PSDADJ 7:0 rw 10.4.8 Attenuation Input Adjustment Register (ATTADJ) The ATTADJ register specifies a value in units of 0.25 dBm to adjust attenuation. This value is added to the result of attenuation measurement for each board ...
Page 197
Configuration Pins Status Register 1 (CONFIG_STS1) • Configuration Pins Status Register 2 (CONFIG_STS2) • SNR for Band 1 (SNR_BAND1) • SNR for Band 2 (SNR_BAND2) • Remote Loss of Frame Counter (R_FR_LOS_CNT) • Channel Failures Counter (FAIL_CNT) • Loss ...
Page 198
General Status Register 2 (GEN_STATUS2) The GEN_STATUS2 register is one of three registers that provide general status information. The others are GEN_STATUS2 General Status Register HRST SRST sc sc Field Bits Typ e HRST 7 sc ...
Page 199
GEN_STATUS3 General Status Register Field Bits Typ e Res 7:3 sc SMII_TXEN 2 sc SAT_FLAG 1 sc MI_FLAG 0 sc 10.5.4 Configuration Pins Status Register 1 (CONFIG_STS1) The fields of the CONFIG_STS1 values of some configuration pins ...
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Field Bits Typ Res 6 r BOOTLINK_E PHY_ADD 4:0 r 10.5.5 Configuration Pins Status Register 2 (CONFIG_STS2) The fields of the CONFIG_STS1 values of some configuration pins after reset. See Reset” on Page ...