PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 53

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 17
Signal Name
RX
TX
REFCLK
TXSYNC
1)
Table 18
Signal Name
RX
RXCLK
RXCLKREF
RXSYNC
RXSYNC_EN
TX
TXCLK
TXSYNC
1)
2.4.2
The Serial Management Interface (SMI) is available in all configurations. This section
shows multiplexed pins used for signals in the following Serial Management Interface
(SMI) modes:
•
•
Preliminary Data Sheet
Pins that control configuration during hard reset must be pulled up or pushed down with resistors, as required.
See
Pins that control configuration during hard reset must be pulled up or pushed down with resistors, as required.
See
MAC –
PHY –
“Configuration Pins During Hard Reset” on Page 81
“Configuration Pins During Hard Reset” on Page 81
Table 20
Table 19
Ethernet Serial Management Interface Modes
Typical SMII Mode Pins
Source Synchronous SMII Mode Pins
Pin Name
ETHOD0
ETHID0
ECLK1
ETHCTLI
Pin Name
ETHOD0
MDCO
ECLK1
ETHCTLO
UTID6
ETHID0
ECLK3
ETHCTLI
Pin #
L9
R12
P12
P13
Pin # I/O
L9
N12
P12
M12
N9
R12
R13
P13
O
O
I
O
I
I
I
I/O
O
I
I
I
53
Description
Reception Data
Configuration pin during hard reset.
Reception Clock
Reference Clock
Reception Synchronization
RXSYNC Synchronization Enable
Transmission Data
Transmission Clock
Transmission Synchronization
Description
Reception Data
Configuration pin during hard reset.
Transmission Data
Reference Clock
Transmission Synchronization
and reference design document for details.
and reference design document for details.
Pin and Signal Descriptions
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827
1)
1)