PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 52

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 15
Signal Name Pin Name
TXD1
TXEN
1)
Table 16
Signal Name
REFCLK
RXD0
RXD1
RXDV
TXD0
TXD1
TXEN
1)
2.4.1.3
Table 17
interface, like MII, with 1-bit wide data buses.
The pin descriptions are identical to MII pin descriptions with the following exceptions:
•
•
Preliminary Data Sheet
Pins that control configuration during hard reset must be pulled up or pushed down with resistors, as required.
See
Pins that control configuration during hard reset must be pulled up or pushed down with resistors, as required.
See
The LSB of MII data buses TXD0 and RXD0 are used as SMII data buses.
The TXD3:TXD1 and RXD3:RXD1 buses are not applicable in an SMII configuration.
“Configuration Pins During Hard Reset” on Page 81
“Configuration Pins During Hard Reset” on Page 81
and
Serial MII Slave Mode
RMII MAC Mode Pins (page 2 of 2)
RMII PHY Mode Pins
Table 18
ETHOD1
ETHCTLO
ETHOD1
ETHCTLO
ETHID0
ETHID1
Pin Name
ECLK1
ETHOD0
ETHCTLI
shows the Serial MII (SMII) interface. SMII is a low pin count
M14
M12
Pin # I/O Function
M10
Pin #
P12
L9
M14
M12
R12
P13
52
O
O
I/O
I
O
O
O
I
I
I
Transmission Data Output
Configuration pin during hard reset.
Transmission Enable
and reference design document for details.
and reference design document for details.
Reference Clock
Reception Data Output
Configuration pin during hard
reset.
Reception Data Output
Configuration pin during hard
reset.
Received Data Valid
Transmission Data Input
Transmission Data Input
Transmission Enable
Function
Pin and Signal Descriptions
1)
1)
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827
1)