PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 195

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 70 Access to Remote Registers
Parameter
REM_16_WR_BT
REM_16_RD_BT
10.4.7
The
the board, in units of 0.25 dB. This value is added to the PSDLEVEL STP opcode VOC
parameter for both carriers that are transmitting.
For example:
•
•
When firmware determines that synthesized impedance is selected (using the
EOC_TCLK
8 db to calibrate the line driver.
PSDADJ
Output PSD Adjustment Register
Preliminary Data Sheet
To add 3 dB to the general PSD output, do the following:
a) Multiply 3 dB x 4 = 12 (or 0C
b) Perform the command <WR 8F0C 0C>
To subtract 4 dB from the general PSD output, do the following:
a) Multiply 4 dB x 4 = 16 (or 10
b) Perform the command <WR 8F0C F0>
PSDADJ
7
PSD Output Adjustment Register (PSDADJ)
configuration pin), it automatically decreases the value of this register by
register specifies a signed value to add to the PSD power level output from
6
VOC_OC
Opcode
xxxx
(
x = number
of bytes to
write.
xxxx
(
x = number
of bytes to
write.
x
x
2
1
H
H
)
)
0010
0001
5
B
B
VOC_DAT Data Fields (Bits 15:0)
Address of Register from Which to Begin to Write
1 through 16 Consecutive Bytes During Boot Link
02
•
•
Note: High and low bytes are reverse of standard.
Address of Register from Which to Begin to Read
1 through 16 Consecutive Bytes During Boot Link
01
•
•
Note: High and low bytes are reverse of standard.
H
H
)
)
H
H
Bits 15:8 specify the low start address.
Bits 7:0 specify the high start address.
Bits 15:8 specify the low start address.
Bits 7:0 specify the high start address.
indicates 16 bytes.
indicates 16 bytes.
4
PSDADJ
(8F0C
195
rw
H
)
3
2
Rev. 1.1, 2005-01-30
Reset Value: 00
1
VDSL6100i
PEF 22827
0
H