PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 43

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 4
Pin or
Ball No.
J12
J14
1)
2)
3)
4)
2.3.4
Table 5
Table 5
Pin or
Ball
No.
M9
M10
N9
N10
R11
P12
P10
R13
P11
R12
N11
M11
P13
Preliminary Data Sheet
Pins that control configuration during hard reset must be pulled up or pushed down with resistors, as required.
See
Pull Down (PD) buffers are 100 K
Pull Up (PU) buffers are 550 K
In the PCM interface, signals J12, J13, J14, H12, H13, H14 and H11 are bits 6 through 0. When the PCM
interface is disabled, signals H11, H12, H13, H14, J12, J13 and J14 are software controlled.
“Configuration Pins During Hard Reset” on Page 81
lists dual purpose pins that support Ethernet.
Name
ETHID3
ETHID1
UTID6
CRSI
COLI
ECLK1
ECLK2
ECLK3
ETHID2
ETHID0
MDCI
Res
ETHCTLI
Ethernet Pins
Name
PCM_TSIG
PCM_TSYNC O
EOC and PCM Pins (page 2 of 2)
Ethernet or Pins (page 1 of 2)
Pin
Type
I
I
I
I
I
I/O
I
I/O
I
I
I
NC
I
Pin
Type
O
Buffer
Type
-
-
-
-
-
-
-
-
-
-
-
-
-
Buffer
Type
PU
-
Function
Network Interface Input Data 3
Network Interface Input Data 1
Source Synchronous SMII Mode –
RXSYNC Signal Synchronization
Carrier Sense Input
Collision Input
Network Interface Clock
Network Interface Clock
Network Interface Clock
Network Interface Input Data 2
Network Interface Input Data 0
MDIO Clock Input
Reserved
Network Interface Control Input
3)
43
Function in Normal Mode
PCM Transmission Serial Signaling
Configuration pin during hard reset.
PCM Transmission Synchronization
Signal
Configuration pin during hard reset.
and reference design document for details.
4)
Pin and Signal Descriptions
Rev. 1.1, 2005-01-30
1)
VDSL6100i
PEF 22827
1)
1)
4)