TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 98

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

B0CSL
(0140H)
B0CSH
(0141H)
MAMR0
(0142H)
MSAR0
(0143H)
(0144H)
(0145H)
MAMR1
(0146H)
MSAR1
(0147H)
(0148H)
(0149H)
MAMR2
(014AH)
MSAR2
(014BH)
(014CH)
(014DH)
MAMR3
(014EH)
MSAR3
(014FH)
BEXCSH
(0159H)
BEXCSL
(0158H)
PMEMCR Bit symbol
(0166H)
B1CSL
B1CSH
B2CSL
B2CSH
B3CSL
B3CSH
Note1: Always write “0”.
Note2: Read-modify-write instruction is prohibited for BnCSL, BnCSH registers (n=0 to 3, EX).
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Read/Write
After reset
M0V20
M0S23
M1V21
M1S23
M2V22
M2S23
M3V22
M3S23
B0E
B1E
B2E
B3E
7
0
1
1
0
1
1
1
1
1
0
1
1
BEXWW2
B0WW2
0 (Note)
B1WW2
0 (Note)
B2WW2
B3WW2
0 (Note)
M0V19
M0S22
M1V20
M1S22
M2V21
M2S22
M3V21
M3S22
B2M
6
0
−
1
1
0
−
1
1
0
0
1
1
0
−
1
1
0
Table 3.6.1 Control Register
BEXWW1
B0WW1
0 (Note)
B1WW1
0 (Note)
B2WW1
0 (Note)
B3WW1
0 (Note)
M0V18
M0S21
M1V19
M1S21
M2V20
M2S21
M3V20
M3S21
W
W
W
W
W
5
1
−
1
1
1
−
1
1
1
−
1
1
1
−
1
1
1
92CM22-96
BEXWW0
B0WW0
B1WW0
B2WW0
B3WW0
B0REC
B1REC
B2REC
B3REC
M0V17
M0S20
M1V18
M1S20
M2V19
M2S20
M3V19
M3S20
OPGE
4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
BEXOM1
OPWR1
B0OM1
B1OM1
B2OM1
B3OM1
M0V16
M0S19
M1V17
M1S19
M2V18
M2S19
M3V18
M3S19
3
0
1
1
0
1
1
0
1
1
0
1
1
0
0
BEXOM0
BEXWR2
OPWR0
B0WR2
B0OM0
B1WR2
B1OM0
B2WR2
B2OM0
B3WR2
B3OM0
M0V15
M0S18
M1V16
M1S18
M2V17
M2S18
M3V17
M3S18
R/W
2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
W
M0V14-V9
M1V15-V9
BEXBUS1
BEXWR1
B0BUS1
B1BUS1
B2BUS1
B3BUS1
B0WR1
B1WR1
B2WR1
B3WR1
M0S17
M1S17
M2V16
M2S17
M3V16
M3S17
PR1
W
W
W
W
W
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
0
1
1
TMP92CM22
2007-02-16
BEXBUS0
BEXWR0
B0BUS0
B1BUS0
B2BUS0
B3BUS0
B0WR0
B1WR0
B2WR0
B3WR0
M0S16
M1S16
M2V15
M2S16
M3V15
M3S16
M0V8
M1V8
PR0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0