TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 164

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

TXD0
ITX0C
(INTTX0 interrupt
request)
Timing of writing
transmission data
SCLK0 output
(<SCLKS> = 1
falling mode)
SCLK0 output
(<SCLKS> = 0
rising mode)
Figure 3.9.19 Transmission Operation in I/O Interface Mode (SCLK0 output mode)
SCLK0 input
(<SCLKS> = 0
rising mode)
SCLK0 input
(<SCLKS> = 1
falling mode)
TXD0
ITX0C
(INTTX0 interrupt
request)
Figure 3.9.20 Transmission Operation in I/O Interface Mode (SCLK0 input mode)
1.
Transmission
TXD0 and SCLK0 pins respectively each time the CPU writes the data to the
transmission buffer. When all data is outputted, INTES0<ITX0C> will be set to
generate the INTTX0 interrupt.
input becomes active after the data has been written to the transmission buffer by
the CPU.
interrupt.
In SCLK output mode 8-bit data and a synchronous clock are output on the
In SCLK input mode, 8-bit data is output from the TXD0 pin when the SCLK0
When all data is outputted, INTES0<ITX0C> will be set to generate INTTX0
Bit0
92CM22-162
Bit0
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
Bit7
TMP92CM22
2007-02-16
(Internal clock
timinig)