TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 159
TMP92xy22FG
Manufacturer Part Number
TMP92xy22FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP92XY22FG.pdf
(260 pages)
Specifications of TMP92xy22FG
Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
32
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
-
Number Of I/o Ports
50
Power Supply Voltage(v)
3.0 to 3.6
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SC1CR
(1209H)
Bit symbol
Read/Write
After reset
Function
Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction.
Received
data bit8
Undefined
Figure 3.9.10 Serial Control Register (for SIO1 and SC1CR)
RB8
7
R
Parity
0: Odd
1: Even
EVEN
6
0
R/W
Parity
addition
0: Disable
1: Enable
92CM22-157
PE
5
0
Overrun
OERR
4
0
R (Cleared to 0 when read)
1: Error
PERR
Parity
3
0
I/O interface input clock selection
Edge selection for SCKL1 pin (I/O mode)
Framing error flag
Parity error flag
Overrun error flag
Parity addition enables
Even parity addition/check
Received data bit8
0
1
0
1
0
1
0
1
Baud rate generator
SCLK1 pin input
Transmits and receives
data on rising edge of SCLK1.
Transmits and receives
data on falling edge of SCLK1.
Disabled
Enabled
Odd parity
Even parity
Framing
FERR
2
0
0: SCLK1
1: SCLK1
SCLKS
1
0
TMP92CM22
R/W
2007-02-16
Cleared to 0
when read
0: Baud rate
1: SCLK1
generator
pin input
IOC
0
0
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