TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 213

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TMP92xy22FG

Manufacturer Part Number
TMP92xy22FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy22FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
32
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
-
Number Of I/o Ports
50
Power Supply Voltage(v)
3.0 to 3.6
3.12 Watchdog Timer (Runaway detection timer)
3.12.1
Internal reset
the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog
timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of
the malfunction.
The TMP92CM22 contains a watchdog timer of runaway detecting.
The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that
Connecting the watchdog timer output to the reset pin internally forces a reset.
(The level of external
Note:
Configuration
f
Figure 3.12.1 is a block diagram of the watchdog timer (WDT).
IO
Care must be exercised in the overall design of the apparatus since the watchdog timer may fail
to function correctly due to external noise, etc.
WDMOD
<WDTP1:0>
Figure 3.12.1 Block Diagram of Watchdog Timer
Binary counter
(22-Stage)
RESET
2
15
Selector
2
Write
4EH
Watchdog timer register
control register WDCR
17
pin is not changed.)
2
Internal data bus
Reset
19
92CM22-211
2
21
Write
B1H
WDMOD<RESCR>
R
Q
WDMOD
<WDTE>
control
Reset
S
Interrupt
request
INTWD
Internal reset
RESET
TMP92CM22
2007-02-16
pin

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