TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 120

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Match with TA0REG
(Value of compare)
Register buffer
TA01RUN
TA01MOD
TA0REG
TA1FFCR
PCCR
PCFC
TA01RUN
X : Don’t care, − : No change
detected when the TA0REG double buffer is enabled.
Therefore n should be set to 7.
Since the low-level period is 36.0 μs when φT1 = (16/fc)s,
set the following value for TA0REG:
2
n
In this mode, the value of the register buffer will be shifted into TA0REG if 2
Use of the double buffer facilitates the handling of low duty ratio waves.
TA0REG
To achieve a 51.2 μs PWM cycle by setting φT1=(16/fc)s (at f
overflow
Example: To output the following PWM waves on the TA1OUT pin at f
51.2 μs/(16/fc)s = 128 = 2
36.0 μs/(16/fc)s = 90 = 5AH
MSB
← −
← 1
← 0
← X
← X
← X
← 1
7
− −
− −
6
X
1
1
X
X
Figure 3.7.18 Operation of Register Buffer
5
X
1
0
X
X
Up counter = Q
4
X
0
1
X
X
X
X
36.0 μs
− − −
− −
−
−
3
1
1
−
51.2 μs
n
2
0
0
X
X
1
92CM22-118
Q
1
0
1
1
1
1
−
1
1
LSB
0
0
1
0
X
−
−
1
Q
2
Stop TMRA0 and clear it to 0.
Select 8-bit PWM mode (cycle: 2
input clock.
Write 5AH.
Clear TA1FF to 0; set inversion to enable.
Set PC1 to TA1OUT pin.
Start TMRA0 counting.
Shift from TA0REG (Register buffer)
C
Up counter = Q
= 40 MHz):
Q
Write to TA0REG
2
7
) and select φT1 as the
C
2
= 40 MHz:
Q
3
TMP92CM22
2007-02-16
n
overflow is