TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 74

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

PD
(0034H)
PDCR
(0036H)
PDFC
(0037H)
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Note 1: Read-modify-write instruction is prohibited for the registers PDFC and PDCR.
Note 2: Can not read the output latch data when PD0 and PD1 are output mode.
7
7
7
6
6
6
Figure 3.5.24 Register for Port D
Port D Function Register
Port D Control Register
5
5
5
Port D Register
92CM22-72
4
4
4
0: Input
1: Output
0: Port
1: TB1OUT1
PD3C
PD3F
PD3
3
3
3
0
0
(Output latch register is set to 1)
0: Input
1: Output
0: Port
1: TB1OUT0
Data from external port
PD2C
PD2F
PD2
2
2
2
0
0
R/W
W
W
0: Input
1: Output
PD2 output setting asTB1OUT0
0: Port
1: TB0IN1
PD3 output setting as TB1OUT1
INT5 Input
PD1C
PD1F
Port D I/O setting
PD1
1
1
1
0
0
PDFC<PD2F>
PDCR<PD2C>
PDFC<PD3F>
PDCR<PD3C>
0
1
Input
Output
0: Input
1: Output
0: Port
1: TB0IN0
INT4 Input
PD0C
PD0F
TMP92CM22
PD0
0
0
0
0
0
2007-02-16
1
1
1
1