TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 4

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TMP92xy22FG

Manufacturer Part Number
TMP92xy22FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy22FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
32
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
-
Number Of I/o Ports
50
Power Supply Voltage(v)
3.0 to 3.6
(4) External memory expansion
(5) Memory controller
(6) 8-bit timers: 4 channels
(7) 16-bit timers: 2 channels
(8) General-purpose serial interface: 2 channels
(9) Serial bus interface: 1 channel
(10) 10-bit AD converter: 8 channels
(11) Watchdog timer
(12) Interrupts: 41 interrupts
(13) Input/output ports: 50 pins (exclude Data bus 8-bit, Address bus 24-bit and
(14) Standby function
(15) Dual-clock controller
(16) Operating voltage
(17) Package
Expandable up to 16 Mbytes (Shared program/data area)
Can simultaneously support 8-/16-bit width external data bus
・・・Dynamic data bus sizing
Separate bus system
Chip select output: 4 channels
UART/synchronous mode
IrDA
I
Clock synchronous mode
Three HALT modes: IDLE2 (Programmable), IDLE1, STOP
PLL: fc = f
Clock gear function: Select a high-frequency clock fc to fc/16
DVCC = 3.0 V to 3.6 V (fc max = 40 MHz)
100-pin QFP: P-LQFP100-1414-0.50F
2
9 CPU interrupts: Software interrupt instruction and illegal instruction
25 internal interrupts: Seven selectable priority levels
7 external interrupts: Seven selectable priority levels (INT0 to INT5 and
C bus mode
OSCH
× 4 (fc = 40 MHz at f
(INT0 to INT3 selectable edge or level interrupt)
92CM22-2
OSCH
= 10 MHz)
RD
TMP92CM22
NMI
pin)
2007-02-16
)

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