TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 28

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

releasing halt
Interrupt of
D0 to D15
A0 to A23
WR
RD
X1
Figure 3.3.8 Timing Chart for STOP Mode Halt State Released by Interrupt
Table 3.3.4 Sample Warm-up Times after Rrelease of STOP Mode
oscillator pin status in STOP mode depends on the settings in the
SYSCR2<SELDRV, DRVE> register. Table 3.3.5, Table 3.3.6 shows the state of
these pins in STOP mode.
warm-up time has elapsed, in order to allow oscillation to stabilize. Warm-up time
set by SYSCR2<WUPTM1:0> register. See the sample warm-up times in Table
3.3.4.
interrupt.
c. STOP mode
When STOP mode is selected, all internal circuits stop, including the internal
After STOP mode has been released system clock output starts when the
Figure 3.3.8 illustrates the timing for release of the STOP mode halt state by an
01 (2
25.6 μ s
8
)
Data
SYSCR2<WUPTM1:0>
92CM22-26
10 (2
1.638 ms
STOP
mode
14
)
Warm-up time
at f
11 (2
6.554 ms
OSCH
16
)
= 10 MHz
TMP92CM22
2007-02-16
Data