TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 253

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

6.
Port Section Equivalent Circuit Diagram
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■
■
Reading the circuit diagram
IC [74HCXX] series.
mode and the CPU executes the HALT instruction. When the drive enable bit <DRVE> is set
to “1”, however, STOP remains at “0”.
ohms.
Data bus (D0 to D7), P1 (D8 to D15), P4 (A0 to A7), P5 (A8 to A15), P6 (A16 to A23),
P76 (
P90 (SCK), PC0 (TA0IN), PC1 (TA1OUT/INT1), PC3 (INT0), PC5 (TA3OUT/INT2), PC6
(TB0OUT/INT3), PD0 (INT4/TB1IN0), PD1 (INT5/TB1IN1), PF1 (RXD0), PF2 (SCLK0/
PF4 (RXD1), and PF5 (SCLK1/
Basically, the gate symbols written are the same as those used for the standard CMOS logic
STOP: This signal becomes active “1” when the halt mode setting register is set to the STOP
The input protection resistance ranges from several tens of ohms to several hundreds of
The dedicated signal is described below.
WAIT
), PD2 (TB1OUT0), PD3 (TB1OUT1), PF6, and PF7
Output data
Output data
Output enable
Output enable
Input data
Input data
Stop
Stop
CTS1
Input enable
92CM22-251
enable
Input
)
VCC
VCC
P-ch
N-ch
P-ch
N
-ch
I/O
I/O
TMP92CM22
2007-02-16
CTS0
),