TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 196

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

(2) Transfer modes
mode.
1.
The SBI0CR1<SIOM1:0> is used to select a transmit, receive or transmit/receive
8-bit transmit mode
SBI0DBR.
start data transfer. The transmitted data is transferred from the SBI0DBR to the
shift register and output, starting with the least significant bit (LSB), via the SO
pin and synchronized with the serial clock. When the transmission data has been
transferred to the shift register, the SBI0DBR becomes empty. The INTSBE0
(Buffer empty) interrupt request is generated to request new data.
wait function will be initiated if new data is not loaded to the data buffer register
after the specified 8-bit data is transmitted. When new transmission data is
written, the automatic wait function is canceled.
new data is shifted. The transfer speed is determined by the maximum delay time
between the time when an interrupt request is generated and the time when data
is written to the SBI0DBR by the interrupt service program.
SO pin holds final bit of the last data until falling edge of the SCK.
INTSBE0 interrupt service program or when the <SIOINH> is set to “1”. When
the <SIOS> is cleared to “0”, the transmitted mode ends when all data is output.
In order to confirm whether data is being transmitted properly by the program,
the <SIOF> to be sensed. The SBI0SR<SIOF> is cleared to “0” when transmission
has been completed. When the <SIOINH> is set to “1”, transmitting datat stops.
The <SIOF> turns “0”.
before new data is shifted; otherwise, dummy data is transmitted and operation
ends.
Set a control register to a transmit mode and write transmission data to the
After the transmit data has been written, set the SBI0CR1<SIOS> to “1” to
When the internal clock is used, the serial clock will stop and the automatic
When the external clock is used, data should be written to the SBI0DBR before
When the transmit is started, after the SBI0SR<SIOF> goes “1” output from the
For stopping data transmission, when the <SIOS> is cleared to “0” by the
When the external clock is used, it is also necessary to clear the <SIOS> to “0”
92CM22-194
TMP92CM22
2007-02-16