TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 245

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

TB1RG0L
TB1RG0H
TB1RG1L
TB1RG1H
TB1FFCR
TB1CP0L
TB1CP0H
TB1CP1L
TB1CP1H
Symbol
TB1MOD
TB1RUN
16-bit timer (2/2)
16-bit timer
16-bit timer
16-bit timer
16-bit timer
register 0
register 0
register 1
register 1
register 0
register 0
register 1
register 1
Timer B1
Timer B1
Timer B1
Capture
Capture
Capture
Capture
Name
register
register
flip-flop
register
control
mode
RUN
high
high
high
high
low
low
low
low
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
119CH
119DH
1198H
119AH
119BH
119EH
119FH
1190H
1192H
RMW)
1193H
RMW)
RMW)
1199H
RMW)
RMW)
RMW)
Invert when
UC12 is
loaded into
TB1CP1H/L
Double
buffer
0: Disable
1: Enable
TB1FF1 inversion
trigger
0: Disable trigger
1: Enable trigger
TB1FF1C1 TB1FF1C0 TB1C1T1
Control TB1FF1
00: Invert
01: Set
10: Clear
11: Don’t care
*Always read as 11.
TB1RDE
TB1CT1
7
0
0
1
R/W
R/W
W*
Invert when
UC12
matches
with
TB1RG1H/L
Always
write “0”.
TB1ET1
6
0
0
1
−
92CM22-243
Invert when
the UC12
value is
loaded in to
TB1CP1H/L.
Software
capture
control
0: Software
1: Undefined
TB0FF0 inversion trigger
0: Disable trigger
1: Enable trigger
TB1CP0I
capture
W
5
1
0
Invert when
the UC12
value is
loaded in to
TB1CP0H/L.
Capture timing
00: Disable
01: TB1N0 ↑ TB1IN1 ↑
10:TB1IN0 ↑ TB1IN0 ↓
11: TA1OUT↑
TB1CPM1 TB1CPM0
TB1C0T1
TA1OUT↓
4
0
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
W
W
W
W
R
R
R
R
Invert when
the UC12
value
matches the
value in
TB1RG1H/L.
IDLE2
0: Stop
1: Operate
TB1E1T1
I2TB0
3
0
0
0
R/W
Invert when
the UC12
value
matches the
value in
TB1RG0H/L.
0: Clear
1: Clear
TMRB1
prescaler
0: Stop and clear
1: Run (Count up)
Up counter
control
TB1PRUN
TB1E0T1
TB1CLE
disable
enable
R/W
2
0
0
0
Timer B1 source clock
00: TB1IN0 pin input
01: φT1
10: φT4
11: φT16
TB1CLK1
Control TB1FF0
00: Invert
01: Set
10: Clear
11: Don’t care
*Always read as 11.
TB1FFC1
1
0
1
TMP92CM22
2007-02-16
W*
UP counter
(UC12)
TB1CLK0
TB1RUN
TB1FFC0
R/W
0
0
0
1