TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 139

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Example: To output a 2 [ms] one-shot pulse with a 3 [ms] delay to the external trigger pulse via the TB1IN0 pin.
TB1RG0H/L ← TB1CP0H/L + 3 ms/φT1
TB1RG1H/L ← TB1RG0H/L + 2 ms/φT1
Setting in Main
TB1MOD
TB1FFCR
PDCR
PDFC
INTE45
INTETB1
TB1RUN
Setting in INT4
TB1FFCR
INTETB1
Setting in INTTB11
TB1FFCR
INTETB1
X : Don’t care, − : No change
value is loaded into capture register (TB1CP0H/L), and set the TB1CP0H/L value (c)
plus the one-shot pulse width (p) to TB0RG1H/L when the interrupt INT4 occurs. The
TB1FF0 inversion should be enable when the up counter (UC12) value matches
TB1RG1H/L, and disabled when generating the interrupt INTTB11.
When delay time is unnecessary, invert timer flip-flop TB1FF0 when up counter
← X X 1 0 1 0 0 1
← X X 0 0 0 0 1 0
← − 0 X X − 1 X 1
← X X − − 1 1 − −
← X 1 0 0 X − − −
← X X − − 0 0 − −
← X 0 0 0 X − − −
← X X X X − 1 − −
← X X X X − 1 X X
← X − − − X 1 0 0
← X 0 0 0 X 0 0 0
* Clock state :
92CM22-137
Set free running.
Count using φT1.
Load into TB1CP0H/L by rising edge of TB1IN0 pin input.
Clear TB1FF0 to 0.
Disable inversion of TB1FF0.
Start TMRB0.
Enable inversion of TB1FF0 when match with
TB1RG0G/L or TB1RG1G/L.
Set INTTB11 to enable.
Disable inversion of TB1FF0 when match with
TB1RG0H/L or TB1RG1H/L.
Disable INTTB11.
Set PD2 to function as the TB1OUT0 pin.
Enable INT4. Disable INTTB10 and INTTB11.
Clock gear 1/1 (fc)
TMP92CM22
2007-02-16