TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 248

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

when write
when write
when read
when read
SBI0DBR
Symbol
SBI0CR1
SBI0CR2
SBI0CR2
SBI0SR
SBI0SR
I2C0AR
(9) I
register 1
Serial bus
Serial bus
Serial bus
Serial bus
2
register2
register2
I
interface
interface
interface
interface
address
C bus/Serial channel (1/2)
Name
register
register
register
register
2
control
control
control
status
status
buffer
C bus0
SBI0
SBI0
(SIO mode)
(I
Address
SIO mode
I
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
2
2
1240H
C mode
1240H
1241H
1242H
1243H
C mode)
1243H
RMW)
RMW)
RMW)
RMW)
RMW)
RMW
0: Slave
1: Master
Number of transfer bits
000: 8
100: 4
Transfer
0: Stop
1: Start
SIOS
MST
BC2
DB7
SA6
7
0
0
0
0
001: 1
101: 5
0: Receive
1: Transmit
Transfer
0: Continue
1: Abort
SIOINH
BC1
DB6
TRX
SA5
W
6
0
0
0
0
010: 2
110: 6
92CM22-246
W
Bus status
monitor
Start/stop
condition
generation
0: Free
1: Busy
0: Start
1: Stop
Transfer mode
00: 8-bit transmit
10: 8-bit transmit/receive
11: 8-bit receive
SIOM1
condition
condition
BC0
DB5
SA4
011: 3
111: 7
BB
5
0
0
0
0
Setting slave address
R (Receiving)/W (Transmission)
0: Request
1: Cancel
Acknowledge
mode
INTSBE0
request
monitor
0: Disable
1: Enable
SIOM0
ACK
R/W
DB4
SA3
PIN
4
0
0
0
1
Undefined
W
W
Arbitration
lost
detection
monitor
0: −
1: Detect
Serial bus interface
operating mode
selection
00: Port mode
01: SIO mode
10: I
11: (Reserved)
Transmit
status monitor
0: Stopped
1: Terminated
Serial bus interface
operating mode
selection
AL/SBIM1
00: Port mode
01: SIO mode
10: I
11: (Reserved)
in progress
SBIM1
SIOF/
DB3
SA2
2
3
0
0
0
2
C bus mode
C bus mode
R/W
Slave
address
match
detection
monitor
0: Undetect
1: Detect
Shift operation
status monitor
0: Stopped
1: Terminated
Setting of the divide value “n”
000: 5
100: 9
111: Reserved
Setting of the divide value “n”
000:4 001:5 010:6 011:7
100:8 101:9 110:10
111:External clock SCK0
in progress
SBIM0
SBIM2
SCK2
SCK2
AAS/
SEF/
DB2
SA1
2
0
0
0
0
0
001: 6
101: 10 110: 11
W
GENERAL
CALL
detection
monitor
0:Undetect
1: Detect
Software reset
generate write “10”
and “01”, then an
internal reset signal is
generated.
Always
write “0”.
SWRST
SCK1
SCK1
AD0/
DB1
SA0
1
0
W
0
0
0
−
0
010: 7
TMP92CM22
2007-02-16
W
Address
recognition
Last
received bit
monitor
0: 0
1: 1
Always
write “0”.
SWRMON
0 :Enable
1: Disable
SWRST0
SCK0/
LARB/
SCK0
R/W
DB0
ALS
011: 8
0/1
0
0
0
0
−
0